Re-purposing byte enables as clock enables for power savings

US2021194827A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2021194827-A1
Application numberUS-201916725901-A
CountryUS
Kind codeA1
Filing dateDec 23, 2019
Priority dateDec 23, 2019
Publication dateJun 24, 2021
Grant date

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

Systems, apparatuses, and methods for efficient data transfer in a computing system are disclosed. A source generates packets to send across a communication fabric (or fabric) to a destination. The source generates partition enable signals for the partitions of payload data. The source negates an enable signal for a particular partition when the source determines the packet type indicates the particular partition should have an associated asserted enable signal in the packet, but the source also determines the particular partition includes a particular data pattern. Routing components of the fabric disable clock signals to storage elements assigned to store the particular partition. The destination inserts the particular data pattern for the particular partition in the payload data.

First claim

Opening claim text (preview).

What is claimed is: 1 . A computing system, comprising: a source comprising circuitry configured to generate a packet comprising: a plurality of partitions of a data payload; and a plurality of enable signals, each associated with a partition of the plurality of partitions; a destination; and a routing component coupled to each of the source and the destination; wherein the routing component comprises circuitry configured to: receive the packet from the source; and disable a clock signal for each storage element of the routing component configured to store data of a given partition of the plurality of partitions, in response to determining the given partition has an associated enable signal in the packet that is negated. 2 . The computing system as recited in claim 1 , wherein the routing component is further configured to convey to the destination: the negated enable signal; and a previous value stored in each storage element assigned to store data of the given partition. 3 . The computing system as recited in claim 1 , wherein the routing component is further configured to enable a clock signal for each storage element of the routing component assigned to store data of the given partition, in response to: determining the given partition has an associated asserted enable signal in the packet. 4 . The computing system as recited in claim 1 , wherein the source is further configured to negate an enable signal for the given partition, in response to: determining a type of the packet indicates the given partition has an associated asserted enable signal in the packet; and determining the given partition comprises a given data pattern. 5 . The computing system as recited in claim 4 , wherein the type of the packet indicating the given partition has an associated asserted enable signal in the packet comprises a response type of packet. 6 . The computing system as recited in claim 1 , wherein the destination is further configured to: receive the packet from the routing component; and insert the given data pattern in the given partition of the packet, in response to: determining a type of the packet indicates the given partition has an associated asserted enable signal in the packet; and determining the given partition has an associated negated enable signal in the packet. 7 . The computing system as recited in claim 1 , wherein the routing component further comprises one of a switch and a repeater of a communication fabric between the source and the destination. 8 . The computing system as recited in claim 1 , wherein the source comprises one or more of a central processing unit, a graphics processing unit and a multimedia engine. 9 . A method, comprising: generating, by a source, a packet comprising: a plurality of partitions of a data payload; and a plurality of enable signals, each associated with a partition of the plurality of partitions; processing, by a destination, the packet; and receiving, by a routing component, the packet from the source; disabling, by the routing component, a clock signal for each storage element of the routing component assigned to store data of a given partition of the plurality of partitions, in response to determining the given partition has an associated negated enable signal in the packet. 10 . The method as recited in claim 9 , further comprising conveying to the destination: the negated enable signal; and a previous value stored in each storage element assigned to store data of the given partition. 11 . The method as recited in claim 9 , further comprising enabling a clock signal for each storage element of the routing component assigned to store data of the given partition, in response to: determining the given partition has an associated asserted enable signal in the packet. 12 . The method as recited in claim 9 , further comprising negating an enable signal for the given partition, in response to: determining a type of the packet indicates the given partition has an associated asserted enable signal in the packet; and determining the given partition comprises a given data pattern. 13 . The method as recited in claim 12 , wherein the type of the packet indicating the given partition has an associated asserted enable signal in the packet comprises a cache victim type of packet. 14 . The method as recited in claim 12 , wherein the type of the packet indicating the given partition has an associated asserted enable signal in the packet comprises a full size write type of packet. 15 . The method as recited in claim 9 , further comprising: receiving, by the destination, the packet from the routing component; and inserting, by the destination, the given data pattern in the given partition of the packet, in response to: determining a type of the packet indicates the given partition has an associated asserted enable signal in the packet; and determining the given partition has an associated negated enable signal in the packet. 16 . The method as recited in claim 9 , wherein the routing component comprises one of a switch and a repeater of a communication fabric between the source and the destination. 17 . An apparatus, comprising: a first interface configured to receive, from a source, a packet comprising: a plurality of partitions of a data payload; and a plurality of enable signals, each associated with a partition of the plurality of partitions; a second interface configured to convey the packet to a destination; a plurality of storage elements; and circuitry configured to: disable a clock signal for each storage element of the plurality of storage elements assigned to store data of a given partition of the plurality of partitions, in response to determining the given partition has an associated negated enable signal in the packet. 18 . The apparatus as recited in claim 17 , wherein the circuitry is further configured to convey, via the second interface, to the destination: the negated enable signal; and a previous value stored in each storage element assigned to store data of the given partition. 19 . The apparatus as recited in claim 17 , wherein the circuitry is further configured to enable a clock signal for each storage element of the plurality of storage elements assigned to store data of the given partition, in response to: determining the given partition has an associated asserted enable signal in the packet. 20 . The apparatus as recited in claim 17 , wherein the apparatus comprises a switch of a communication fabric between the source and the destination.

Assignees

Inventors

Classifications

  • Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

  • Grouping or interlacing selector groups or stages · CPC title

  • Parsing or analysis of headers · CPC title

  • for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS] · CPC title

  • for storage area networks · CPC title

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US2021194827A1 cover?
Systems, apparatuses, and methods for efficient data transfer in a computing system are disclosed. A source generates packets to send across a communication fabric (or fabric) to a destination. The source generates partition enable signals for the partitions of payload data. The source negates an enable signal for a particular partition when the source determines the packet type indicates the p…
Who is the assignee on this patent?
Advanced Micro Devices Inc
What technology area does this patent fall under?
Primary CPC classification H04L49/25. Mapped technology areas include Electricity.
When was this patent published?
Publication date Thu Jun 24 2021 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).