Memory controllers and memory systems including the same

Patent metadata

Field	Value
Publication number	US-2021194508-A1
Application number	US-202016987554-A
Country	US
Kind code	A1
Filing date	Aug 7, 2020
Priority date	Dec 23, 2019
Publication date	Jun 24, 2021
Grant date	—

Abstract

A memory controller includes an error correction circuit and a central processing unit (CPU) to control the error correction circuit. The error correction circuit includes an error correction code (ECC) decoder and a memory to store a parity check matrix. The ECC decoder performs an ECC decoding on a codeword read from the memory module to: (i) generate a first syndrome and a second syndrome, (ii) generate a decoding mode flag associated with a type of errors in the codeword based on the second syndrome and a decision syndrome, (iii) operate in one of a first decoding mode and a second decoding mode based on the decoding mode flag, and (iv) selectively correct one of a chip error associated with one of the data chips and one or more symbol errors in the codeword.

First claim

What is claimed is:

1 . An error correction circuit, comprising:
an error correction code (ECC) decoder configured to:
perform an ECC decoding on a codeword read from a memory module to generate a first syndrome and a second syndrome;
generate a decoding mode flag associated with a type of error(s) in the codeword based on the second syndrome and a decision syndrome;
operate in one of a first decoding mode and a second decoding mode based on the decoding mode flag; and
selectively correct one of a chip error and one or more symbol errors in the codeword, the chip error being associated with a data chip in the memory module.

2 . The error correction circuit of claim 1 , wherein the ECC decoder is further configured to:
operate in the first decoding mode in response to: (i) the second syndrome indicating that the codeword includes one symbol error, and (ii) the first syndrome being non-zero; and correct the one symbol error.

3 . The error correction circuit of claim 1 , wherein the ECC decoder is further configured to:
operate in the first decoding mode in response to: (i) the second syndrome indicating that the codeword includes two symbol errors having the same pattern, and (ii) the first syndrome being non-zero; and correct the two symbol errors.

4 . The error correction circuit of claim 1 , wherein the ECC decoder is further configured to:
operate in the first decoding mode in response to: (i) the second syndrome indicating that the codeword includes two symbol errors having different and random patterns, and (ii) the first syndrome being non-zero; and correct the two symbol errors.

5 . The error correction circuit of claim 1 , wherein the ECC decoder is further configured to:
operate in the second decoding mode in response to: (i) the second syndrome indicating that the codeword includes three or more symbol errors, (ii) the first syndrome being non-zero, and (iii) the second decoding mode corresponding to a chip-kill mode; determine that the three or more symbol errors occur in a first data chip within the memory module; and correct user data provided from the first data chip.

6 . The error correction circuit of claim 5 , wherein when a symbol error occurs in a second data chip within the memory module, which is different from the first data chip, after the ECC decoder corrects the three or more symbol errors in the user data provided from the first data chip, the ECC decoder operates in the first decoding mode to correct the symbol error in user data provided from the second data chip using a parity check matrix.

7 . The error correction circuit of claim 1 , wherein the memory module includes a plurality of data chips, a first parity chip and a second parity chip; and wherein:
the codeword includes a user data set, a first parity data and a second parity data; the user data set is read from the plurality of data chips; the first parity data is read from the first parity chip; and the first second parity data is read from the second parity chip, and wherein a parity check matrix within a memory within the error correction circuit includes: a first check matrix, which is generated based on Reed-Solomon code and is used for generating the first syndrome; and a second check matrix, which is generated based on a simple parity check code and is used for generating the second syndrome.

8 . The error correction circuit of claim 7 , wherein the ECC decoder is further configured to:
generate the first syndrome by performing a matrix-multiplication operation on the codeword and the first check matrix; and generate the second syndrome by performing a simple parity check on the codeword using the second check matrix.

9 . The error correction circuit of claim 7 , wherein:
the first check matrix includes a plurality of Galois field sub matrixes corresponding to the data chips and the first parity chip, and each of the plurality of Galois field sub matrixes has p×p elements, p being an integer greater than three; and the second check matrix includes a plurality of unit sub matrixes corresponding to the data chips and, the first parity chip and the second parity chip, and each of the plurality of unit sub matrixes has p×p elements.

10 . The error correction circuit of claim 9 , wherein each of the of unit sub matrixes includes a plurality of unit matrixes arranged in a diagonal direction, with each of the plurality of unit matrixes having q×q elements, q being an integer greater than one and smaller than p.

11 . The error correction circuit of claim 1 , wherein the ECC decoder includes:
a syndrome generation circuit configured to generate the first syndrome based on the codeword using a first parity check matrix, generate the second syndrome based on the codeword using a second parity check matrix, and generate the decoding mode flag based on the first syndrome and the second syndrome; a first decoder configured to correct the chip error in the codeword based on the first syndrome and the second syndrome to provide a first output data set; a second decoder configured to correct the one or more symbol errors in the codeword based on the first syndrome to provide a second output data set; and a selection circuit configured to select one of the first output data set and the second output data set to output a corrected user data set.

12 . The error correction circuit of claim 11 , wherein the syndrome generation circuit includes:
a first syndrome generator configured to generate the first syndrome by performing a matrix-multiplication operation on the codeword and the first parity check matrix; a second syndrome generator configured to generate the second syndrome by performing a simple parity check on the codeword using the second parity check matrix; and a flag generator configured to generate the decoding mode flag indicating the type of errors based on the first syndrome and the second syndrome.

13 . The error correction circuit of claim 11 , wherein the first decoder is configured to:
generate a plurality of sub syndromes corresponding to respective one of the plurality of data chips based on the second syndrome and the parity check matrix; and determine a data chip in which the chip error occurs, among the plurality of data chips, based on comparison of the sub syndromes and the first syndrome.

14 . The error correction circuit of claim 1 , further comprising an ECC encoder configured to:
perform ECC encoding on a user data set to generate a first parity data and a second parity data using a parity generation matrix; and provide the memory module with a codeword including the user data set, the first parity data and the second parity data.

15 . The error correction circuit of claim 14 , wherein the parity generation matrix includes a first parity generation matrix and a second parity generation matrix; and wherein the ECC encoder is configured to:
generate the first parity data by performing a matrix-multiplication operation on the user data set and the first parity generation matrix; and generate the second parity data by performing a simple parity check on the user data set and the first parity data using the second parity generation matrix.

16 . A memory system, comprising:
a memory module having a plurality of data chips, a first parity chip and a second parity chip therein; and a memory controller configured to control the memory module, the memory controller comprising:
an error correction circuit comprising an error correction code (ECC) decoder and a memory configured to store a parity check matrix, said

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Sungrae
• Lee Kijun
• Lee Myungkyu
• Cho Sunghye
• Kim Chanki
• Song Yeonggeol

Classifications

• G06F11/1048

  using arrangements adapted for a specific error detection or correction feature · CPC title

• G06F11/1044 Primary

  with specific ECC/EDC distribution · CPC title

• G06F11/1012 Primary

  using codes or arrangements adapted for a specific type of error (G06F11/1048 takes precedence) · CPC title

• G06F11/108

  Parity data distribution in semiconductor storages, e.g. in SSD · CPC title

• G11C29/52

  Protection of memory contents; Detection of errors in memory contents · CPC title