Memory device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-2021193736-A1
Application number	US-202117173865-A
Country	US
Kind code	A1
Filing date	Feb 11, 2021
Priority date	Feb 22, 2016
Publication date	Jun 24, 2021
Grant date	—

Abstract

A method of manufacturing a memory device includes sequentially forming and then etching a preliminary selection device layer, a preliminary middle electrode layer, and a preliminary variable resistance layer on a substrate, thereby forming a selection device, a middle electrode, and a variable resistance layer. At least one of a side portion of the selection device or a side portion of the variable resistance layer is removed so that a first width of the middle electrode in a first direction parallel to a top of the substrate is greater than a second width of the variable resistance layer in the first direction or a third width of the selection device in the first direction. A capping layer is formed on at least one of a side wall of the etched side portion of the selection device or a side wall of the etched side portion of the variable resistance layer.

First claim

What is claimed is:

1 . A semiconductor device comprising:
a substrate; a driving circuit region disposed on the substrate and including a plurality of peripheral circuits; a plurality of word lines disposed on the driving circuit region, and including a first word line and a second word line; a plurality of memory cell structures disposed on the plurality of word lines, and including a first memory cell structure that is disposed on the first word line, a second memory cell structure that is disposed on the first word line, a third memory cell structure that is disposed On the second word line and a fourth memory cell structure that is disposed on the second word line; a plurality of bit lines disposed on the plurality of memory cell structures, and including a first bit line that is disposed on the first memory cell structure and on the third memory cell structure and a second bit line that is disposed on the second memory cell structure and on the fourth memory cell structure; and a plurality of insulating patterns disposed between two adjacent memory cell structures among the plurality of memory cell structures, and including a first insulating pattern disposed between the first memory cell structure and second memory cell structure and a second insulating pattern disposed between the first memory cell structure and the third memory cell structure, wherein the first memory cell structure includes a first electrode, a selection device disposed on the first electrode, a second electrode disposed on the selection device, a variable resistance layer disposed on the second electrode and a third electrode disposed on the variable resistance layer, and a void is disposed in at least one of the plurality of insulating patterns.

2 . The semiconductor device of claim 1 , wherein a width of the selection layer is greater than a width of the variable resistance layer.

3 . The semiconductor device of claim 1 , wherein the first memory cell structure includes a first capping layer disposed on a sidewall of the selection device and a second capping layer disposed on a sidewall of the variable resistance layer.

4 . The semiconductor device of claim 3 , wherein a width of the first capping layer is less than a width of the second capping layer.

5 . The semiconductor device of claim 1 , wherein the first insulating pattern includes the void.

6 . The semiconductor device of claim 1 , wherein a width of the selection layer is less than a width of the first word line.

7 . The semiconductor device of claim 1 , wherein the variable resistance layer includes a magnetic tunnel junction (MJT) structure that includes two electrodes including a magnetic material and a dielectric disposed between the two electrodes.

8 . A semiconductor device comprising:
a substrate; a plurality of word lines disposed on the substrate, and including a first word line and a second word line; a plurality of memory cell structures disposed on the plurality of word lines, and including a first memory cell structure that is disposed on the first word line, a second memory cell structure that is disposed on the first word line, a third memory cell structure that is disposed on the second word line and a fourth memory cell structure that is disposed on the second word line; a plurality of bit lines disposed on the plurality of memory cell structures, and including a first bit line that is disposed on the first memory cell structure and on the third memory cell structure and a second bit line that is disposed on the second memory cell structure and on the fourth memory cell structure; and a plurality of insulating patterns disposed between two adjacent memory cell structures among the plurality of memory cell structures, and including a first insulating pattern disposed between the first memory cell structure and the second memory cell structure, wherein the first memory cell structure includes a first electrode, a selection device disposed on the first electrode, a second electrode disposed on the selection device, a variable resistance layer disposed on the second electrode, a third electrode disposed on the variable resistance layer, a first capping layer disposed on a sidewall of the selection device and a second capping layer disposed on a sidewall of the variable resistance layer, and a width of the selection layer is greater than a width of the variable resistance layer.

9 . The semiconductor device of claim 8 , further comprising a driving circuit region disposed between the substrate and the plurality of word lines, and including a plurality of peripheral circuits.

10 . The semiconductor device of claim 8 , wherein a width of the first capping layer is less than a width of the second capping layer.

11 . The semiconductor device of claim 8 , wherein the selection device includes at least one from Si, Te, As, Ge or In.

12 . The semiconductor device of claim 8 , wherein the semiconductor device is a magnetic random access memory (MRAM).

13 . The semiconductor device of claim 8 , wherein an air spacer is disposed in at least one of the plurality of insulating patterns

14 . The semiconductor device of claim 13 , wherein the first insulating pattern includes the air spacer.

15 . A semiconductor device comprising:
a substrate; a driving circuit region disposed on the substrate and including a plurality of peripheral circuits; a plurality of word lines disposed on the driving circuit region, and including a first word line and a second word line; a plurality of memory cell structures disposed on the plurality of word lines, and including a first memory cell structure that is disposed on the first word line, a second memory cell structure that is disposed on the first word line, a third memory cell structure that is disposed on the second word line and a fourth memory cell structure that is disposed on the second word line; a plurality of bit lines disposed on the plurality of memory cell structures, and including a first bit line that is disposed on the first memory cell structure and on the third memory cell structure and a second bit line that is disposed on the second memory cell structure and on the fourth memory cell structure; and a plurality of insulating patterns disposed between two adjacent memory cell structures among the plurality of memory cell structures, and including a first insulating pattern disposed between the first memory cell structure and the second memory cell structure, wherein the first memory cell structure includes a first electrode, a selection device disposed on the first electrode, a second electrode disposed on the selection device, a variable resistance layer disposed on the second electrode, a third electrode disposed on the variable resistance layer, a first capping layer disposed on a sidewall of the selection device and a second capping layer disposed on a sidewall of the variable resistance layer, and a width of the selection layer is greater than a width of the variable resistance layer.

16 . The semiconductor device of claim 15 , wherein a width of the first capping layer is less than a width of the second capping layer.

17 . The semiconductor device of claim 15 , wherein a width of the first capping layer is substantially the same as a width of the second capping layer.

18 . The semiconductor device of claim 15 , wherein the variable resistance layer includes one or more elements from periodic table Group VI, and one or more chemical modifiers from Group III, IV or V.

19 . The semiconducto

Assignees

• Samsung Electronics Co Ltd

Inventors

• Seong Dong-Jun
• Park Soon-Oh

Classifications

• H10D84/01

  Manufacture or treatment · CPC title

• H01L45/06

  Electricity · mapped topic

• H01L45/1233

  Electricity · mapped topic

• H01L27/2427 Primary

  Electricity · mapped topic

• H01L45/1246

  Electricity · mapped topic