Display device and manufacturing method thereof

US2021193697A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2021193697-A1
Application numberUS-202016918759-A
CountryUS
Kind codeA1
Filing dateJul 1, 2020
Priority dateDec 20, 2019
Publication dateJun 24, 2021
Grant date

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

A display device includes: a substrate; a gate insulating layer disposed on the substrate; a semiconductor layer disposed on the gate insulating layer and including a first semiconductor; a source electrode and a drain electrode disposed on the first semiconductor; and a data line disposed on the gate insulating layer, wherein the gate insulating layer includes a first portion overlapping the data line in a plan view and a second portion disposed adjacent to the first portion, and the second portion is thinner than the first portion.

First claim

Opening claim text (preview).

What is claimed is: 1 . A display device comprising: a substrate; a gate insulating layer disposed on the substrate; a semiconductor layer disposed on the gate insulating layer and including a first semiconductor; a source electrode and a drain electrode disposed on the first semiconductor; and a data line disposed on the gate insulating layer, wherein the gate insulating layer includes a first portion overlapping the data line in a plan view and a second portion disposed adjacent to the first portion, and wherein the second portion is thinner than the first portion. 2 . The display device of claim 1 , wherein the first semiconductor has an edge parallel to an edge of the source electrode and disposed outside the edge of the source electrode in the plan view. 3 . The display device of claim 2 , wherein the gate insulating layer is disposed between the data line and the substrate, and the semiconductor layer is absent in an area where the gate insulating layer is disposed between the data line and the substrate. 4 . The display device of claim 3 , further comprising a gate line disposed on the substrate and crossing the data line, wherein the semiconductor layer further includes a second semiconductor disposed at a region where the gate line and the data line cross each other. 5 . The display device of claim 3 , wherein the source electrode includes a straight line portion extending in a direction different from an extending direction of the data line and a curved portion extending from the straight line portion, wherein the semiconductor layer further includes a first protruded portion having a shape protruded from one side of the first semiconductor, and wherein the first protruded portion of the semiconductor layer overlaps at least a part of the straight line portion of the source electrode. 6 . The display device of claim 5 , wherein the first protruded portion of the semiconductor layer has an edge parallel to an edge of the part of the straight line portion of the source electrode. 7 . The display device of claim 6 , further comprising a gate line disposed on the substrate and crossing the data line, wherein the gate line includes a gate electrode, and wherein the first protruded portion of the semiconductor layer overlaps an edge of the gate electrode. 8 . The display device of claim 6 , further comprising a gate line disposed on the substrate and crossing the data line, wherein the semiconductor layer further includes a second protruded portion having a shape protruded from one side of the first semiconductor, and wherein the second protruded portion of the semiconductor layer overlaps an edge of the gate line. 9 . The display device of claim 8 , wherein the second protruded portion of the semiconductor layer has an edge parallel to an edge of at least a first portion of the drain electrode away from a second portion that overlaps the first semiconductor. 10 . The display device of claim 8 , further comprising a storage electrode disposed between the substrate and the gate insulating layer, wherein the drain electrode includes an expanded portion overlapping the storage electrode, and wherein the semiconductor layer is absent between the expanded portion of the drain electrode and the substrate. 11 . A display device comprising: a substrate; a gate line disposed on the substrate; a gate insulating layer disposed on the gate line; a semiconductor layer disposed on the gate insulating layer and including a first semiconductor; a source electrode and a drain electrode that are disposed on the first semiconductor; and a data line disposed on the gate insulating layer, wherein the first semiconductor has an edge parallel to an edge of the source electrode and disposed outside the edge of the source electrode in a plan view, wherein the semiconductor layer is absent between the data line and the substrate, and wherein the semiconductor layer further includes a second semiconductor disposed at a region where the gate line and the data line cross each other. 12 . The display device of claim 11 , wherein the source electrode includes a straight line portion extending in a direction different from an extending direction of the data line and a curved portion extending from the straight line portion, wherein the semiconductor layer further includes a first protruded portion having a shape protruded from one side of the first semiconductor, and wherein the first protruded portion of the semiconductor layer overlaps at least a part of the straight line portion of the source electrode. 13 . The display device of claim 12 , wherein the first protruded portion of the semiconductor layer has an edge parallel to an edge of the part of the straight line portion of the source electrode. 14 . The display device of claim 13 , wherein the gate line includes a gate electrode, and wherein the first protruded portion of the semiconductor layer overlaps an edge of the gate electrode. 15 . The display device of claim 13 , wherein the semiconductor layer further includes a second protruded portion having a shape protruded from one side of the first semiconductor, and wherein the second protruded portion of the semiconductor layer overlaps an edge of the gate line. 16 . The display device of claim 15 , wherein the second protruded portion of the semiconductor layer has an edge parallel to an edge of at least a first portion of the drain electrode away from a second portion of the drain electrode that overlaps the first semiconductor. 17 . A manufacturing method of a display device comprising: forming a gate line including a gate electrode on a substrate; forming a gate insulating layer on the gate line; forming a semiconductor layer on the gate insulating layer and etching the semiconductor layer to form a first opening; depositing a conductive material on the semiconductor layer to form a conductive layer and etching the conductive layer by using a first mask pattern to form a data line and an electrode; and etching the semiconductor layer by using the first mask pattern or a second mask pattern that includes a portion of the first mask pattern, wherein the data line is formed at a position overlapping the first opening, and wherein an edge of the first opening and an edge of the data line are spaced apart from each other. 18 . The manufacturing method of claim 17 , wherein the first mask pattern includes a first portion and a second portion having different thicknesses from each other, wherein the second mask pattern excludes the first portion that is thinner than the second portion, and wherein the manufacturing method further comprising etching the electrode by using the second mask pattern to form a source electrode and a drain electrode facing each other. 19 . The manufacturing method of claim 18 , further comprising forming a storage electrode line including a storage electrode on the substrate, wherein a second opening is further formed in the semiconductor layer in the etching of the semiconductor layer to form the first opening, wherein the drain electrode includes an expanded portion overlapping the storage electrode, wherein the expanded portion is formed at a position overlapping the second opening, and wherein an edge of the second opening and an edge of the expanded portion of the drain electrode are spaced apart from each other. 20 . The manufacturing method of claim 18 , wherein, in the etching of the semiconductor

Assignees

Inventors

Classifications

  • characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

  • characterised by the active materials · CPC title

  • having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device · CPC title

  • H10D86/441Primary

    Interconnections, e.g. scanning lines · CPC title

  • comprising manufacture, treatment or coating of substrates · CPC title

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US2021193697A1 cover?
A display device includes: a substrate; a gate insulating layer disposed on the substrate; a semiconductor layer disposed on the gate insulating layer and including a first semiconductor; a source electrode and a drain electrode disposed on the first semiconductor; and a data line disposed on the gate insulating layer, wherein the gate insulating layer includes a first portion overlapping the d…
Who is the assignee on this patent?
Samsung Display Co Ltd
What technology area does this patent fall under?
Primary CPC classification H10D86/441. Mapped technology areas include Electricity.
When was this patent published?
Publication date Thu Jun 24 2021 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).