3d semiconductor device and structure

Patent metadata

Field	Value
Publication number	US-2021193626-A1
Application number	US-202117174344-A
Country	US
Kind code	A1
Filing date	Feb 11, 2021
Priority date	Apr 19, 2015
Publication date	Jun 24, 2021
Grant date	—

Abstract

A 3D semiconductor device, the device including: a first die including first transistors and a first interconnect; a second die including second transistors and a second interconnect; and a third die including third transistors and a third interconnect, where the first die is overlaid by the second die, where the first die is overlaid by the third die, where the first die has a first die area and the second die has a second die area, where the first die area is at least 20% larger than the second die area, where the second die is pretested, where the second die is bonded to the first die, where the bonded includes metal to metal bonding, where the first die includes at least two first alignment marks positioned close to a first die edge of the first die, and where the third die is bonded to the first die.

First claim

We claim:

1 . A 3D semiconductor device, the device comprising:
a first die comprising first transistors and a first interconnect; a second die comprising second transistors and a second interconnect; and a third die comprising third transistors and a third interconnect,
wherein said first die is overlaid by said second die,
wherein said first die is overlaid by said third die,
wherein said first die has a first die area and said second die has a second die area,
wherein said first die area is at least 20% larger than said second die area,
wherein said second die is pretested,
wherein said second die is bonded to said first die,
wherein said bonded comprises metal to metal bonding,
wherein said first die comprises at least two first alignment marks positioned close to a first die edge of said first die, and
wherein said third die is bonded to said first die.

2 . The 3D semiconductor device according to claim 1 ,
wherein said second die is aligned to said first die with less than 800 nm alignment error.

3 . The 3D semiconductor device according to claim 1 ,
wherein said bonded comprises hybrid bonding.

4 . The 3D semiconductor device according to claim 1 ,
wherein said second die comprises an array of memory cells, wherein said first die comprises a control logic to control reads and writes to said array of memory cells.

5 . The 3D semiconductor device according to claim 1 ,
wherein said second die comprises at least two second alignment marks positioned close to a second die edge of said second die.

6 . The 3D semiconductor device according to claim 1 , further comprising:
a through second die via having a diameter of less than 400 nm.

7 . A 3D semiconductor device, the device comprising:
a first die comprising first transistors and a first interconnect; a second die comprising second transistors and a second interconnect; and a third die comprising third transistors and a third interconnect,
wherein said first die is overlaid by said second die,
wherein said first die is overlaid by said third die,
wherein said second die is bonded to said first die,
wherein said bonded comprises hybrid bonding,
wherein said first die comprises at least two first alignment marks positioned close to a first die edge of said first die, and
wherein said third die is bonded to said first die.

8 . The 3D semiconductor device according to claim 7 ,
wherein said first die has a first die area and said second die has a second die area, and wherein said first die area is at least 20% larger than said second die area.

9 . The 3D semiconductor device according to claim 7 , further comprising:
a through second die via having a diameter of less than 400 nm.

10 . The 3D semiconductor device according to claim 7 ,
wherein said second die is aligned to said first die with less than 800 nm alignment error.

11 . The 3D semiconductor device according to claim 7 ,
wherein said first wafer has a first diameter greater than 280 mm, and wherein said second die is sourced from a second wafer with a second diameter less than 240 mm.

12 . The 3D semiconductor device according to claim 7 ,
wherein said second die comprises at least two second alignment marks positioned close to a second die edge of said second die.

13 . The 3D semiconductor device according to claim 7 ,
wherein said second die comprises an array of memory cells, wherein said first die comprises a control logic to control reads and writes to said array of memory cells, and wherein said control logic comprises memory decoders.

14 . A 3D semiconductor device, the device comprising:
a first die comprising first transistors and a first interconnect; a second die comprising second transistors and a second interconnect; and a third die comprising third transistors and a third interconnect,
wherein said first die is overlaid by said second die,
wherein said first die is overlaid by said third die,
wherein said second die is bonded to said first die,
wherein said bonded comprises hybrid bonding,
wherein said second die comprises an array of memory cells,
wherein said first die comprises a control logic, and
wherein said third die is bonded to said first die.

15 . The 3D semiconductor device according to claim 14 ,
wherein said control logic controls reads and writes to said array of memory cells.

16 . The 3D semiconductor device according to claim 14 , further comprising:
a through second die via having a diameter of less than 400 nm.

17 . The 3D semiconductor device according to claim 14 ,
wherein said second die is aligned to said first die with less than 800 nm alignment error.

18 . The 3D semiconductor device according to claim 14 ,
wherein said first die has a first die area and said second die has a second die area, wherein said first die area is at least 20% larger than said second die area.

19 . The 3D semiconductor device according to claim 14 ,
wherein said first die comprises at least two first alignment marks positioned close to a first die edge of said first die, wherein said second die comprises at least two second alignment marks positioned close to a second die edge of said second die.

20 . The 3D semiconductor device according to claim 14 ,
wherein said first die is sourced from a first wafer with a diameter greater than 280 mm, and wherein said second die is sourced from a second wafer with a diameter less than 240 mm.

Assignees

• Monolithic 3D Inc

Inventors

• Or-Bach Zvi

Classifications

• H10W70/682

  comprising holes having chips therein · CPC title

• H10W90/284

  characterised by structural arrangements for measuring or testing · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/20

  Configurations of stacked chips · CPC title

• H10W72/0198

  batch processes · CPC title