Array substrates and display devices
US-2024347681-A1 · Oct 17, 2024 · US
US2021187910A1 · US · A1
| Field | Value |
|---|---|
| Publication number | US-2021187910-A1 |
| Application number | US-201816757727-A |
| Country | US |
| Kind code | A1 |
| Filing date | Oct 24, 2018 |
| Priority date | Oct 27, 2017 |
| Publication date | Jun 24, 2021 |
| Grant date | — |
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A sub-assembly includes a glass substrate, a plurality of electronic devices, and a passivation layer. The glass substrate includes a first surface, a second surface opposite to the first surface, and a third surface extending between the first surface and the second surface. The glass substrate includes a plurality of laser damaged regions extending from the first surface to the second surface. The plurality of electronic devices are on the first surface of the glass substrate. The passivation layer is on the plurality of electronic devices and the third surface of the glass substrate. The passivation layer includes an opening to each laser damaged region of the plurality of laser damaged regions.
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What is claimed is: 1 . A sub-assembly comprising: a glass substrate comprising a first surface, a second surface opposite to the first surface, and a third surface extending between the first surface and the second surface, the glass substrate comprising a plurality of laser damaged regions extending from the first surface to the second surface; a plurality of electronic devices on the first surface of the glass substrate; and a passivation layer on the plurality of electronic devices and the third surface of the glass substrate, the passivation layer comprising an opening to each laser damaged region of the plurality of laser damaged regions. 2 . The sub-assembly of claim 1 , wherein the passivation layer is on the second surface of the glass substrate. 3 . The sub-assembly of claim 1 , wherein the plurality of laser damaged regions are configured to be etched to impart a plurality of corresponding through glass vias. 4 . The sub-assembly of claim 1 , wherein the passivation layer comprises one of a resin material, a polyimide material, an acrylic material, and an inorganic material. 5 . The sub-assembly of claim 1 , wherein the passivation layer has a thickness between 1 μm and 50 μm. 6 . The sub-assembly of claim 1 , wherein the plurality of electronic devices comprises a plurality of thin-film electronic devices. 7 . The sub-assembly of claim 1 , further comprising: a plurality of electronic devices on the second surface of the glass substrate. 8 . A method for fabricating a glass component, the method comprising: laser damaging a glass substrate to create a plurality of laser damaged regions extending from a first surface of the glass substrate to a second surface of the glass substrate opposite to the first surface; fabricating a plurality of electronic devices on the first surface of the glass substrate; applying a protective material over the plurality of electronic devices and a third surface of the glass substrate extending between the first surface and the second surface of the glass substrate; and etching the plurality of laser damaged regions to impart a corresponding plurality of through glass vias. 9 . The method of claim 8 , further comprising: metalizing the plurality of through glass vias to create a corresponding plurality of electrical signal paths extending from the first surface to the second surface of the glass substrate. 10 . The method of claim 9 , further comprising: removing the protective material. 11 . The method of claim 8 , wherein etching the plurality of laser damaged regions comprises wet etching the plurality of laser damaged regions. 12 . The method of claim 8 , further comprising: fabricating a plurality of electronic devices on the second surface of the glass substrate. 13 . The method of claim 8 , where laser damaging the glass substrate precedes fabricating the plurality of electronic devices on the first surface of the glass substrate. 14 . The method of claim 8 , wherein applying the protective material comprises applying one of a resin material, a polyimide material, an acrylic material, and an inorganic material. 15 . The method of claim 8 , wherein applying the protective material comprises applying the protective material to a thickness between 1 μm and 50 μm. 16 . The method of claim 8 , wherein laser damaging the glass substrate comprises irradiating the glass substrate with a carbon dioxide laser with a wavelength between 9 μm and 10.2 μm. 17 . The method of claim 8 , wherein laser damaging the glass substrate comprises irradiating the glass substrate with an ultraviolet laser with a wavelength between 300 nm and 400 nm. 18 . A method for fabricating a display, the method comprising: laser damaging a glass substrate to create a plurality of laser damaged regions extending from a first surface of the glass substrate to a second surface of the glass substrate opposite to the first surface; fabricating an array of thin-film transistors on the first surface of the glass substrate; applying a protective material over the array of thin-film transistors and over a third surface of the glass substrate extending between the first surface and the second surface of the glass substrate; etching the plurality of laser damaged regions to impart a corresponding plurality of through glass vias; metalizing the plurality of through glass vias to create a corresponding plurality of electrical contacts extending through the glass substrate and coupled to the array of thin-film transistors; and removing the protective material. 19 . The method of claim 18 , further comprising: electrically coupling each electrical contact to a control board. 20 . The method of claim 18 , further comprising: electrically coupling a light source to each thin-film transistor of the array of thin-film transistors.
by forming openings in the dielectric parts · CPC title
characterised by the compositions or shapes of the interlayer dielectrics · CPC title
Interconnections, e.g. scanning lines · CPC title
comprising manufacture, treatment or coating of substrates · CPC title
Two-dimensional arrangements, e.g. asymmetric LED layout · CPC title
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