Interrupt signaling for a memory device

Patent metadata

Field	Value
Publication number	US-2021181990-A1
Application number	US-202017116180-A
Country	US
Kind code	A1
Filing date	Dec 9, 2020
Priority date	Dec 16, 2019
Publication date	Jun 17, 2021
Grant date	—

Abstract

Methods, systems, and devices for interrupt signaling for a memory device are described. A memory device may transmit an interrupt signal to a host device to alter a sequence of operations that would otherwise be executed by the host device. The memory device may transmit the interrupt signal in response to detecting an error condition at the memory device, a performance degradation at the memory device, or another trigger event. In some examples, the memory device may include a dedicated interrupt pin for transmitting interrupt signals. Alternatively, the memory device may transmit interrupt signals via a pin also sued to transmit error detection codes. For example, the memory device may transmit an interrupt signal before or after an error detection code or may invert the error detection code to indicate the interrupt, in which case the inverted error detection code may act as an interrupt signal.

First claim

What is claimed is:

1 . A method, comprising:
receiving, at a memory device, a read command for data stored at the memory device; transmitting, based at least in part on receiving the read command, the data via a first interface; and transmitting, based at least in part on receiving the read command, an indication of an interrupt via a second interface.

2 . The method of claim 1 , further comprising:
transmitting, based at least in part on the read command, an error detection code for the data via the second interface.

3 . The method of claim 2 , wherein the indication of the interrupt is transmitted via the second interface before the error detection code is transmitted via the second interface.

4 . The method of claim 3 , wherein the indication of the interrupt is transmitted via the second interface after at least a portion of the data is transmitted via the first interface.

5 . The method of claim 2 , wherein the indication of the interrupt is transmitted via the second interface after the error detection code is transmitted via the second interface.

6 . The method of claim 2 , wherein the indication of the interrupt and the error detection code are transmitted concurrently via the second interface.

7 . The method of claim 6 , further comprising:
determining the error detection code based at least in part on the data; and determining a bitwise inversion of the error detection code; wherein concurrently transmitting the indication of the interrupt and the error detection code comprises transmitting the bitwise inversion of the error detection code.

8 . The method of claim 2 , wherein the second interface comprises an error detection code (EDC) pin.

9 . The method of claim 1 , wherein the second interface comprises a pin dedicated to carrying indications of interrupts.

10 . The method of claim 1 , further comprising:
receiving, after transmitting the indication of the interrupt, a request for information via a third interface; and transmitting, based at least in part on the request, an indication of a value of an operating parameter for the memory device via the third interface.

11 . The method of claim 10 , wherein the third interface comprises a Joint Test Action Group (JTAG) interface.

12 . The method of claim 1 , wherein the interrupt is configured to alter a sequence of operations by a host device for the memory device.

13 . The method of claim 1 , wherein the first interface comprises a data interface.

14 . A method, comprising:
transmitting, to a memory device, a read command for data; receiving, based at least in part on the read command, the data via a first interface; receiving, based at least in part on the read command, an indication of an interrupt via a second interface; and altering a sequence of operations based at least in part on receiving the indication of the interrupt via the second interface.

15 . The method of claim 14 , further comprising:
receiving, based at least in part on the read command, an error detection code for the data via the second interface.

16 . The method of claim 15 , wherein the indication of the interrupt is received via the second interface before the error detection code is received via the second interface.

17 . The method of claim 16 , wherein the indication of the interrupt is received via the second interface after at least a portion of the data is received via the first interface.

18 . The method of claim 15 , wherein the indication of the interrupt is received via the second interface after the error detection code is received via the second interface.

19 . The method of claim 15 , wherein the indication of the interrupt and the error detection code are received concurrently via the second interface.

20 . The method of claim 19 , further comprising:
determining a second error detection code based at least in part on the data; determining that the error detection code is a bitwise inversion of the second error detection code; and identifying the error detection code as comprising the indication of the interrupt based at least in part on the error detection code being the bitwise inversion of the second error detection code.

21 . The method of claim 15 , wherein the second interface comprises an error detection code pin, or wherein the second interface comprises a pin dedicated to carrying indications of interrupts.

22 . The method of claim 15 , further comprising:
transmitting, after receiving the indication of the interrupt, a request for information via a third interface; and receiving, based at least in part on the request, an indication of a value of an operating parameter for the memory device via the third interface.

23 . An apparatus, comprising:
a memory array operable to store data; a command address interface operable to receive an access command associated with the data; a data interface operable to exchange the data with the memory array; and a third interface operable to transmit an indication of an interrupt based at least in part on the access command and a condition of the apparatus.

24 . The apparatus of claim 23 , further comprising:
an error detection component coupled with the third interface and operable to determine an error detection code for the data, wherein the third interface comprises an error detection code pin.

25 . The apparatus of claim 24 , further comprising:
an interrupt component coupled with the error detection code pin and operable to transmit a signal via the error detection code pin before or after the error detection code is transmitted via the error detection code pin, the signal comprising the indication of the interrupt.

26 . The apparatus of claim 24 , further comprising:
an interrupt component coupled with the error detection code pin and operable to invert bits of the error detection code, wherein the indication of the interrupt comprises the inverted bits of the error detection code.

27 . The apparatus of claim 23 , wherein the third interface comprises a pin dedicated to transmitting indications of interrupts.

Assignees

• Micron Technology Inc

Inventors

• Balb Markus
• Hein Thomas
• Hoenigschmid Heinz

Classifications

• G06F3/0619

  in relation to data integrity, e.g. data losses, bit errors · CPC title

• G06F3/0659 Primary

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title