Micro semiconductor device and micro semiconductor display

Patent metadata

Field	Value
Publication number	US-2021175391-A1
Application number	US-202117179845-A
Country	US
Kind code	A1
Filing date	Feb 19, 2021
Priority date	Dec 4, 2018
Publication date	Jun 10, 2021
Grant date	—

Abstract

A micro semiconductor device and a micro semiconductor display are provided. The micro semiconductor device includes an epitaxial structure, a first electrode, a second electrode and a supporting layer. The epitaxial structure has a bottom surface and a top surface, wherein the bottom surface is defined as a central region and a peripheral region. A first electrode and a second electrode are disposed on the central region of the bottom surface of the epitaxial structure, or the first electrode is disposed on the central region of the bottom surface of the epitaxial structure and the second electrode is disposed on the top surface of the epitaxial structure. The supporting layer is disposed on the peripheral region of the bottom surface of the epitaxial structure.

First claim

What is claimed is:

1 . A micro semiconductor device, comprises:
an epitaxial structure having a bottom surface and a top surface, wherein the bottom surface is defined as a central region and a peripheral region; a first electrode and a second electrode, wherein the first electrode and the second electrode are disposed on the central region of the bottom surface of the epitaxial structure, or the first electrode is disposed on the central region of the bottom surface of the epitaxial structure and the second electrode is disposed on the top surface of the epitaxial structure; and a supporting layer, wherein the supporting layer is disposed on the peripheral region of the bottom surface of the epitaxial structure.

2 . The micro semiconductor device as claimed in claim 1 , wherein the supporting layer does not contact the first electrode and the second electrode.

3 . The micro semiconductor device as claimed in claim 1 , the first electrode and second electrode have a first height H 1 , the supporting layer has a second height H 2 , and the ratio (H 1 /H 2 ) of the first height H 1 to the second height H 2 is 0.8 to 1.2.

4 . The micro semiconductor device as claimed in claim 1 , wherein the supporting layer is discontinuously arranged on the peripheral region.

5 . The micro semiconductor device as claimed in claim 4 , wherein the supporting layer comprises a first portion and a second portion, and the central region is disposed between an orthogonal projection of the first portion onto the bottom surface of the epitaxial structure and an orthogonal projection of the second portion onto the bottom surface of the epitaxial structure.

6 . The micro semiconductor device as claimed in claim 5 , wherein the first electrode and the second electrode are disposed on the bottom surface of the epitaxial structure, an orthogonal projection of the first electrode onto the bottom surface has a first center, an orthogonal projection of the second electrode onto the bottom surface has a second center, and an orthogonal projection of the first portion onto the bottom surface of the epitaxial structure and an orthogonal projection of the second portion onto the bottom surface of the epitaxial structure simultaneously overlap an extension line passing through the first center and the second center.

7 . The micro semiconductor device as claimed in claim 1 , wherein the supporting layer is continuously arranged on the peripheral region.

8 . The micro semiconductor device as claimed in claim 7 , wherein an orthogonal projection of the supporting layer onto the bottom surface of the epitaxial structure surrounds the central region.

9 . The micro semiconductor device as claimed in claim 1 , further comprising a filling layer disposed on the central region of the bottom surface of the epitaxial structure.

10 . The micro semiconductor device as claimed in claim 9 , wherein the first electrode and the second electrode are disposed on the bottom surface of the epitaxial structure, and the filling layer is disposed between the first electrode and the second electrode.

11 . The micro semiconductor device as claimed in claim 9 , wherein the filling layer directly contacts the first electrode and the second electrode.

12 . The micro semiconductor device as claimed in claim 9 , wherein the filling layer does not directly contact the first electrode and the second electrode.

13 . The micro semiconductor device as claimed in claim 9 , wherein the filling layer has a third height H 3 , and the ratio (H 1 /H 3 ) of the first height H 1 to the third height H 3 is 0.8 to 1.2.

14 . A micro semiconductor display, comprising:
a display substrate having a top surface; a plurality of contact pads disposed on the tot surface of the display substrate; a plurality of the micro semiconductor devices as claimed in Claim 1 , wherein each of the first electrodes of the epitaxial structure is directly bonded with one of the contact pads.

15 . The micro semiconductor display as claimed in claim 14 , wherein a part of the first electrode is disposed between the support layer and the contact pad.

16 . The micro semiconductor display as claimed in claim 15 , wherein a cross-section of the first electrode is L-shape.

17 . The micro semiconductor display as claimed in claim 14 , wherein an orthogonal projection of the supporting layer onto the display substrate overlaps an orthogonal projection of the contact pad onto the display substrate.

18 . The micro semiconductor display as claimed in claim 14 , wherein each of the second electrodes is disposed on the central region of the bottom surface of the epitaxial structure and directly bonded with one of the contact pads.

19 . The micro semiconductor display as claimed in claim 18 , wherein a part of the second electrode is disposed between the supporting layer and the contact pad.

20 . The micro semiconductor display as claimed in claim 19 , wherein a cross-section of the second electrode is L-shape.

Assignees

• Playnitride Display Co Ltd

Inventors

• Liu Ying-Tsang
• Chen Pei-Hsin
• Shih Yi-Chun
• Chen Yi-Ching
• Li Yu-Chu
• Lin Tzu-Yang
• Lai Yu-Hung

Classifications

• H10W90/00 Primary

  Package configurations · CPC title

• H10H29/142

  Two-dimensional arrangements, e.g. asymmetric LED layout · CPC title

• H10H20/857

  Interconnections, e.g. lead-frames, bond wires or solder balls · CPC title

• H10H20/831

  characterised by their shape · CPC title

• H10H20/84

  Coatings, e.g. passivation layers or antireflective coatings · CPC title