Image processing apparatus and image processing method

Patent metadata

Field	Value
Publication number	US-2021160492-A1
Application number	US-201816639196-A
Country	US
Kind code	A1
Filing date	May 22, 2018
Priority date	Aug 23, 2017
Publication date	May 27, 2021
Grant date	—

Abstract

An image processing apparatus and an image processing method are provided. The image processing apparatus includes: a division control unit that, on the basis of a first boundary dividing an image into a plurality of partial areas, further sets a second boundary and divides each of the partial areas into a plurality of slices; and an encoding unit that encodes the image on the basis of the first boundary and the second boundary, in which the division control unit sets the second boundary such that the plurality of slices included in the partial area has unequal numbers of lines, and the slice situated at the bottom among the plurality of slices included in the partial area is not a slice having the most lines in the partial area.

First claim

1 . An image processing apparatus comprising:
a division control unit that, on a basis of a first boundary dividing an image into a plurality of partial areas, further sets a second boundary and divides each of the partial areas into a plurality of slices; and an encoding unit that encodes the image on a basis of the first boundary and the second boundary, wherein the division control unit sets the second boundary such that the plurality of slices included in the partial area has unequal numbers of lines, and the slice situated at a bottom among the plurality of slices included in the partial area is not a slice having most lines in the partial area.

2 . The image processing apparatus according to claim 1 , wherein
the image processing apparatus further comprises a plurality of chips, each of the chips has a plurality of cores, and the cores have a function of the encoding unit.

3 . The image processing apparatus according to claim 2 , wherein
the core encodes one of the slices specified on a basis of the first boundary and the second boundary, and the chip encodes one of the partial areas.

4 . The image processing apparatus according to claim 3 , wherein the division control unit sets the second boundary according to an amount of transfer, between the chips, of decoded image data related to the slice situated at the bottom.

5 . The image processing apparatus according to claim 4 , wherein the amount of transfer is specified on a basis of hierarchical search information or image feature amount information.

6 . The image processing apparatus according to claim 4 , wherein in a case where the decoded image data of the slice situated at the bottom is not transferred between the chips, the division control unit sets the second boundary such that the plurality of slices included in the partial area has equal numbers of lines.

7 . The image processing apparatus according to claim 6 , wherein in a case where the image is not to be a referenced frame, the division control unit sets the second boundary such that the plurality of slices included in the partial area has equal numbers of lines.

8 . The image processing apparatus according to claim 1 , wherein the division control unit sets the second boundary such that the number of lines in each of the plurality of slices included in the partial area is an integer multiple of a number of vertical pixels of a coding unit.

9 . The image processing apparatus according to claim 8 , wherein the division control unit sets the second boundary such that the number of lines in each of the plurality of slices included in the partial area is an integer multiple of a number of vertical pixels of a largest coding unit.

10 . An image processing method comprising:
on a basis of a first boundary dividing an image into a plurality of partial areas, further setting a second boundary and dividing each of the partial areas into a plurality of slices; and encoding the image on a basis of the first boundary and the second boundary, wherein the second boundary is set such that the plurality of slices included in the partial area has unequal numbers of lines, and the slice situated at a bottom among the plurality of slices included in the partial area is not a slice having most lines in the partial area.

Assignees

• Sony Semiconductor Solutions Corp

Inventors

• Tanaka Masao
• Kimura Tsuyoshi
• Yasuda Mikita
• Tsuchiya Toshiharu
• Chaki Yasuyuki

Classifications

• H04N19/156

  Availability of hardware or computational resources, e.g. encoding based on power-saving criteria · CPC title

• H04N19/172

  the region being a picture, frame or field · CPC title

• H04N19/119 Primary

  Adaptive subdivision aspects, e.g. subdivision of a picture into rectangular or non-rectangular coding blocks · CPC title

• H04N19/51

  Motion estimation or motion compensation · CPC title

• H04N19/174

  the region being a slice, e.g. a line of blocks or a group of blocks · CPC title