Wireless Power System

Patent metadata

Field	Value
Publication number	US-2021143688-A1
Application number	US-202017073699-A
Country	US
Kind code	A1
Filing date	Oct 19, 2020
Priority date	Nov 11, 2019
Publication date	May 13, 2021
Grant date	—

Abstract

A method of over-current protection in a wireless power receiver operating in a high-power mode includes digitally receiving an output current signal, generating an OC INT signal if the output current signal is greater than a current limit value, and if the OC INT signal is generated, transmitting Count A number of End Power Transfer (EPT) packets. If wireless power transmission has not stopped, transmitting Count C number of Control Error Packets (CEPs) with Value B. If wireless power transmission has not reduced such that the output current IL is below the current limit value, then enabling an LDO current limit circuit in a power block of the wireless power receiver. In a low-power mode, the receiver enables a hardware over-current circuit that generates an OC INT signal when the output current exceeds a current limit.

First claim

What is claimed is:

1 . A method of over-current protection in a wireless power receiver, comprising:
in a high-power mode,
receiving an output current signal from an analog-to-digital converter;
comparing the output current signal with a current limit value;
generating an OC INT signal if the output current signal is greater than the current limit value; and
if the OC INT signal is generated, transmitting Count A number of End Power Transfer (EPT) packets.

2 . The method of claim 1 , wherein Count A is a value between 0 and FFh, wherein a value A=0 disables transmission of EPT packets and a value A=FFh indicates repeated transmissions of the EPT packets.

3 . The method of claim 1 , wherein Count A is set to a A default value.

4 . The method of claim 1 , wherein Count A is set by a user input to the wireless power receiver.

5 . The method of claim 1 , further including in the high-power mode
determining whether wireless power transmission has stopped; and if wireless power transmission has not stopped, transmitting Count C number of Control Error Packets (CEPs) with Value B.

6 . The method of claim 5 , wherein Count C is a value between 0 and FFh wherein a value of C=0 disables transmission of CEPs and a value of A=FFh indicates repeated transmission of CEPs.

7 . The method of claim 5 , wherein Count C is set to a C default value.

8 . The method of claim 5 , wherein Count C is set by a user input to the wireless power receiver.

9 . The method of claim 5 , wherein Value B is a number between −128 and 0.

10 . The method of claim 5 , wherein Value B is set to a B default value.

11 . The method of claim 5 , wherein Value B is set by a user input to the wireless power receiver.

12 . The method of claim 5 , wherein if wireless power transmission has not reduced such that the output current IL is below the current limit value, then enabling an LDO current limit circuit in a power block of the wireless power receiver.

13 . The method of claim 1 , wherein in a low-power mode the wireless power receiver enables a hardware over-current circuit that generates an OC INT signal when the output current exceeds a current limit.

14 . The method of claim 13 , wherein the wireless power receiver operates in low-power mode or in high-power mode according to a user input parameter.

15 . The method of claim 13 , wherein the wireless power receiver operates in low power mode or in high power mode according to whether the output current is above or below a transition value.

16 . The method of claim 15 , wherein the transition value is set by a user input to the wireless power receiver.

17 . A wireless power receiver, comprising:
a rectifier receiving power from a receiver coil and producing a rectified voltage; a power block coupled to receive the rectified voltage and provide an output voltage, the power block further providing an output current IL; an amplitude shift key (ASK) modulator coupled to transmit digital data packets on the power on the receiver coil; an analog-to-digital converter coupled to provide a digitized output current IL from the output current IL; and a processor coupled to control the rectifier and the power block, coupled to transmit data packets through the ASK modulator, and coupled to receive the digitized output current IL, the processor executing instructions to, in a high-power mode,
compare the digitized output current IL with a current limit value,
generate an OC INT signal if the output current signal is greater than the current limit value, and
transmit Count A number of End Power Transfer (EPT) packets if the OC INT signal is generated.

18 . The wireless power receiver of claim 17 , wherein Count A is a value between 0 and FFh, wherein a value A=0 disables transmission of EPT packets and a value A=FFh indicates repeated transmissions of the EPT packets.

19 . The wireless power receiver of claim 17 , wherein Count A is set to a A default value.

20 . The wireless power receiver of claim 17 , further including an interface coupled to the processor and wherein Count A is set by a user input to the wireless power receiver.

21 . The wireless power receiver of claim 17 , wherein the processor further executes instructions in the high-power mode to
determine whether wireless power transmission has stopped; and transmit Count C number of Control Error Packets (CEPs) with Value B if wireless power transmission has not stopped.

22 . The wireless power receiver of claim 21 , wherein Count C is a value between 0 and FFh wherein a value of C=0 disables transmission of CEPs and a value of A=FFh indicates repeated transmission of CEPs.

23 . The wireless power receiver of claim 21 , wherein Count C is set to a C default value.

24 . The wireless power receiver of claim 21 , further including an interface coupled to the processor and wherein Count C is set by a user input to the wireless power receiver.

25 . The wireless power receiver of claim 21 , wherein Value B is a number between −128 and 0.

26 . The wireless power receiver of claim 21 , wherein Value B is set to a B default value.

27 . The wireless power receiver of claim 21 , further including an interface coupled to the processor and wherein Value B is set by a user input to the wireless power receiver.

28 . The wireless power receiver of claim 21 , further including an LDO limit circuit in the power block wherein the processor further executes instructions to enable the LDO current limit circuit in a power block of the wireless power receiver if wireless power transmission has not reduced such that the output current IL is below the current limit value.

29 . The wireless power receiver of claim 17 , further including a hardware over-current circuit that receivers the output current IL and provides an over-current interrupt signal if the output current IL exceeds a current limit and wherein the processor executes instructions to
disable the hardware over-current circuit in high-power mode; and enable the hardware over-current circuit in a low-power mode.

30 . The wireless power receiver of claim 29 , further including an interface coupled to the processor and wherein the wireless power receiver operates in low-power mode or in high-power mode according to a user input parameter.

31 . The wireless power receiver of claim 29 , wherein the process executes instructions to operate in low power mode or operate in high power mode according to whether the output current IL is above or below a transition value.

Assignees

• Renesas Electronics America Inc

Inventors

• Agrawal Pooja
• Dzebic Adnan
• Qi Tao
• Jaycox Steve
• Jeong Chan Young

Classifications

• H02J2105/44

  Portable electronic devices · CPC title

• H02J7/92

  with prioritisation of loads or sources · CPC title

• H02J7/02

  for charging batteries from AC mains by converters · CPC title

• H02H1/0007

  concerning the detecting means (in general G01R or other subclasses of G01; reed switches H01H71/2445) · CPC title

• H02J50/10 Primary

  using inductive coupling · CPC title