Display Device and System

Patent metadata

Field	Value
Publication number	US-2021141221-A1
Application number	US-202017097291-A
Country	US
Kind code	A1
Filing date	Nov 13, 2020
Priority date	Nov 13, 2019
Publication date	May 13, 2021
Grant date	—

Abstract

A logic circuit comprising a logic sub-circuit arranged to output a stream, S1, of Fresnel lens values, F(x), of a Fresnel lens for display on [m×n] pixels of a pixelated display device. In a first step, the logic circuit is arranged to set an initial data value stored in a first data register unit of the logic sub-circuit to (a−k) 2 and set an initial data value stored in a second data register unit of the logic sub-circuit to a 2 −(a−k) 2 . In a second step the logic circuit is arranged to read the initial data value stored in the first data register unit and the initial data value stored in the second data register unit in a first iteration, and to read the data value stored in the first data register unit in the preceding iteration and the data value stored in the second data register unit in the preceding iteration, in a further iteration. In a third step, the logic circuit is arranged to sum the data value read from the first data register unit and the data value read from the second data register unit to form x 2 . In a fourth step, the logic circuit is arranged to calculate F(x) based on x 2 . In a fifth step, the logic circuit is arranged to output F(x) as the next value in the stream of F(x) values. In a sixth step, the logic circuit is arranged to write x 2 to the first data register unit. In a seventh step, the logic circuit is arranged to add 2k 2 to the value stored in the second data register unit. In an eighth step, the logic circuit is arranged to perform further iterations that repeat the second to seventh steps for x=a+k, a+2k, a+3k . . . a+(n−1)k, wherein a is the starting value of x, k is an increment in x and F(a) is the first value of stream, S1.

First claim

1 . A logic circuit comprising a logic sub-circuit arranged to output a stream, S1, of Fresnel lens values, F(x), of a Fresnel lens for display on [m×n] pixels of a pixelated display device, wherein the logic circuit is arranged to:
(a) set an initial data value stored in a first data register unit of the logic sub-circuit to (a−k) 2 and set an initial data value stored in a second data register unit of the logic sub-circuit to a 2 −(a−k) 2 ;
(b) in a first iteration, read the initial data value stored in the first data register unit and the initial data value stored in the second data register unit, or in a further iteration, read the data value stored in the first data register unit in the preceding iteration and the data value stored in the second data register unit in the preceding iteration;
(c) sum the data value read from the first data register unit and the data value read from the second data register unit to form x 2 ;
(d) calculate F(x) based on x 2 ;
(e) output F(x) as the next value in the stream of F(x) values;
(f) write x 2 to the first data register unit;
(g) add 2k 2 to the value stored in the second data register unit; and
(h) perform further iterations that repeat steps (b) to (g) for x=a+k, a+2k, a+3k . . . a+(n−1)k, wherein a is the starting value of x, k is an increment in x and F(a) is the first value of stream, S1.

2 . A logic circuit as claimed in claim 1 comprising a plurality, k, of logic sub-circuits, wherein the plurality of logic sub-circuits are arranged in parallel and each logic sub-circuit is arranged to output a respective stream, S1, S2 . . . Sk, of Fresnel lens values, F(x), by performing steps (a) to (h) using a respective value of a, wherein the streams, S1, S2 . . . Sk, correspond to a=x 1 , x 1 +1, x 1 +2 . . . x 1 +(k−1), respectively.

3 . A logic circuit as claimed in claim 1 wherein x 1 =−n/2 or x 1 =1−n/2.

4 . A logic circuit as claimed in claim 1 wherein F(x) is calculated based on x 2 using the following equation:

F
⁡

(
x
)

=

π
⁢

⁢

p
x
2

f
x

⁢
λ

⁢

x
2

wherein f x is the focal length of the Fresnel lens in the x-direction, k is the wavelength of light and p x is the pixel size of the pixelated display device in the x-direction.

5 . A logic circuit as claimed in claim 1 wherein the first data register unit comprises a first input register, a first data register and a first multiplexer for selecting between a data value stored in the first input register and a data value stored in the first data register, and the second data register unit comprises a second input register, a second data register and a second multiplexer for selecting between a data value stored in the second input register and a data value stored in the second data register, wherein the logic circuit is further arranged to:
provide a reset signal to the first and second multiplexers in the first iteration of step (b), in order to select the initial data values stored in the respective first and second input registers, and
not provide a reset signal to the first and second multiplexers in further iterations of step (b), in order to select the data values stored in the respective first and second data registers in the preceding iteration.

6 . A logic circuit as claimed in claim 1 further arranged to output a stream of Fresnel lens values, F(y), of the Fresnel lens, wherein the logic circuit is arranged to perform the following steps iteratively for y=b, b+1, b+2, . . . (b+m−1):
(i) if y=b, set an initial data value stored in a first further data register unit to (b−1) 2 and set an initial data value stored in a second further data register unit to b 2 −(b−1) 2 ;
(j) if y=b, read the initial data value stored in the first further data register unit of the logic circuit and the initial data value stored in the second further data register unit of the logic circuit, or if y≠b, read the data value stored in the first further data register unit in the preceding iteration and the data value stored in the second further data register unit in the preceding iteration;
(k) sum the data value read from the first further data register unit and the data value read from the second further data register unit to form y 2 ;
(l) calculate F(y) based on y 2 ;
(m) output F(y) as the next value in the stream of F(y) values;
(n) write y 2 to the first further data register unit; and
(o) add two to the value stored in the second further data register unit, wherein b is the starting value of y and F(b) is the first value of the stream of Fresnel lens values, F(y).

7 . A logic circuit as claimed in claim 6 wherein b=−m/2 or 1−m/2.

8 . A logic circuit as claimed in claim 6 wherein the logic circuit is arranged to calculate F(y) based on y 2 using the following equation:

F
⁡

(
y
)

=

π
⁢

⁢

p
y
2

f
y

⁢
λ

⁢

y
2

wherein f y is the focal length of the Fresnel lens in the y-direction, λ is the wavelength of light and p y is the pixel size of the pixelated display device in the y-direction.

9 . A logic circuit as claimed in claim 6 wherein step (m) outputs the value F(y) as the next n values in the stream of F(y) values.

10 . A logic circuit as claimed in claim 6 further arranged to sum each F(x) value with a corresponding F(y) value in order to form a stream of Fresnel lens values, F(x,y), for each pixel.

11 . A logic device comprising the logic circuit as claimed in claim 10 , wherein the device comprises an application specific integrated circuit, ASIC, or a programmable logic device, PLD, optionally a field programmable gate array, FPGA.

12 . A holographic projector comprising:
the device of claim 11 ; a pixelated display device arranged to display a light modulation pattern comprising the Fresnel lens pattern in accordance with the stream of Fresnel lens values, F(x,y); and a light source arranged to illuminate the light modulation pattern with light having a wavelength, λ.

Assignees

• Dualitas Ltd

Inventors

• Collin Mikael

Classifications

• G03H1/0808

  Methods of numerical synthesis, e.g. coherent ray tracing [CRT], diffraction specific · CPC title

• G06F7/552

  Powers or roots {, e.g. Pythagorean sums} · CPC title

• G06F17/141 Primary

  Discrete Fourier transforms · CPC title

• G06F7/5443

  Sum of products (for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00) · CPC title

• G03H2226/02

  Computing or processing means, e.g. digital signal processor [DSP] · CPC title