Semiconductor devices and methods for forming the same

Patent metadata

Field	Value
Publication number	US-2021135082-A1
Application number	US-202016999966-A
Country	US
Kind code	A1
Filing date	Aug 21, 2020
Priority date	Nov 6, 2019
Publication date	May 6, 2021
Grant date	—

Abstract

A semiconductor device is provided. The semiconductor device includes a substrate. The semiconductor device also includes a semiconductor layer disposed in the substrate. The semiconductor device further includes a first dielectric layer disposed on the semiconductor layer. The semiconductor device includes a second dielectric layer disposed on the first dielectric layer. The semiconductor device also includes a pair of thermopiles disposed on the second dielectric layer. The first dielectric layer and the second dielectric layer form a chamber.

First claim

What is claimed is:

1 . A semiconductor device, comprising:
a substrate; a semiconductor layer disposed in the substrate; a first dielectric layer disposed on the semiconductor layer; a second dielectric layer disposed on the first dielectric layer; and a pair of thermopiles disposed on the second dielectric layer; wherein the first dielectric layer and the second dielectric layer form a chamber.

2 . The semiconductor device as claimed in claim 1 , wherein the semiconductor layer is a heavily doped N-type semiconductor layer or a heavily doped P-type semiconductor layer.

3 . The semiconductor device claimed in claim 2 , wherein a concentration of the semiconductor layer is greater than 1E16 cm −3 .

4 . The semiconductor device as claimed in claim 1 , wherein a material of the pair of thermopiles comprises an N-type semiconductor and a P-type semiconductor.

5 . The semiconductor device as claimed in claim 1 , wherein the chamber is disposed in the substrate.

6 . The semiconductor device as claimed in claim 1 , further comprising:
a semiconductor element disposed in the substrate and adjacent to the pair of thermopiles and the chamber.

7 . The semiconductor device as claimed in claim 6 , wherein the semiconductor element is separated from the pair of thermopiles and the chamber by the first dielectric layer and the second dielectric layer.

8 . A semiconductor device, comprising:
a substrate having a chamber; a dielectric layer surrounding the chamber; a semiconductor layer disposed at a bottom of the dielectric layer; and a pair of thermopiles disposed on the dielectric layer.

9 . The semiconductor device as claimed in claim 8 , wherein the dielectric layer comprises:
a first dielectric layer disposed at sidewalls and a bottom of the chamber; and a second dielectric layer disposed at a top of the chamber.

10 . The semiconductor device as claimed in claim 8 , wherein the semiconductor layer is a heavily doped N-type semiconductor layer or a heavily doped P-type semiconductor layer.

11 . The semiconductor device as claimed in claim 10 , wherein a concentration of the semiconductor layer is greater than 1E16 cm −3 .

12 . The semiconductor device as claimed in claim 8 , wherein a material of the pair of thermopiles comprises an N-type semiconductor and a P-type semiconductor.

13 . A method for forming semiconductor devices, comprising:
providing a substrate; forming a recess in the substrate; forming a semiconductor layer at a bottom of the recess; forming a first dielectric layer in the recess; forming a filling structure to fill the recess; forming a second dielectric layer on the filling structure; forming a pair of thermopiles on the second dielectric layer; and removing the filling structure to form a chamber.

14 . The method for manufacturing a semiconductor device as claimed in claim 13 , wherein the semiconductor layer is formed by ion implantation.

15 . The method for manufacturing a semiconductor device as claimed in claim 13 , wherein the semiconductor layer is a heavily doped N-type semiconductor layer or a heavily doped P-type semiconductor layer.

16 . The method for manufacturing a semiconductor device as claimed in claim 15 , wherein a concentration of the semiconductor layer is greater than 1E16 cm −3 .

17 . The method for manufacturing a semiconductor device as claimed in claim 13 , wherein a material of the pair of thermopiles comprises an N-type semiconductor and a P-type semiconductor.

18 . The method for manufacturing a semiconductor device as claimed in claim 13 , wherein an outermost side of the semiconductor layer and an outermost side of first dielectric layer in the recess are separated from each other in a direction parallel to a bottom surface of the substrate.

19 . The method for manufacturing a semiconductor device as claimed in claim 13 , further comprising:
forming a semiconductor element in the substrate and adjacent to the pair of thermopiles and the chamber, wherein the semiconductor element is separated from the pair of thermopiles and the chamber by the first dielectric layer and the second dielectric layer.

20 . The method for manufacturing a semiconductor device as claimed in claim 19 , wherein the pair of thermopiles is formed before the forming of the semiconductor element.

Assignees

• Nuvoton Technology Corp

Inventors

• Chiu In-Shiang
• Chen Kuang-Chu
• Hsiao Peng-Chan
• Liu han-ying

Classifications

• G01K7/028

  using microstructures, e.g. made of silicon · CPC title

• H01L35/32 Primary

  Electricity · mapped topic

• H01L35/34

  Electricity · mapped topic

• H10N10/17 Primary

  characterised by the structure or configuration of the cell or thermocouple forming the device · CPC title

• H10N10/01 Primary

  Manufacture or treatment · CPC title