Image processing apparatus and display apparatus

Patent metadata

Field	Value
Publication number	US-2021134252-A1
Application number	US-201816769848-A
Country	US
Kind code	A1
Filing date	Nov 30, 2018
Priority date	Dec 6, 2017
Publication date	May 6, 2021
Grant date	—

Abstract

A configuration of an image processing apparatus is simplified. In a display apparatus, a first sub input image and a second sub input image are input to a first back-end processor, and a first residual input image and a second residual input image are input to a second back-end processor. A first entire input image is constituted by combining the first sub input image and the first input image. In a case where the display apparatus processes the first entire input image, the first back-end processor processes the first sub input image, and the second back-end processor processes the first residual input image.

First claim

1 . An image processing apparatus comprising:
a first image processor; and a second image processor, wherein a first entire input image is constituted by combining a first sub input image and a first residual input image, wherein a second entire input image is constituted by combining a second sub input image and a second residual input image, wherein the first sub input image and the second sub input image are input to the first image processor, wherein the first residual input image and the second residual input image are input to the second image processor, wherein the image processing apparatus processes one of the first entire input image and the second entire input image, wherein, in a case where the image processing apparatus processes the first entire input image,
the first image processor processes the first sub input image, and the second image processor processes the first residual input image, and
wherein, in a case where the image processing apparatus processes the second entire input image,
the first image processor processes the second sub input image, and the second image processor processes the second residual input image.

2 . The image processing apparatus according to claim 1 ,
wherein, in the first entire input image,
a boundary of the first sub input image that is adjacent to the first residual input image is set as a first sub input boundary image, and
a boundary of the first residual input image that is adjacent to the first sub input image is set as a first residual input boundary image,
wherein, in a case where the image processing apparatus processes the first entire input image,
the first image processor supplies the first sub input boundary image to the second image processor,
the second image processor supplies the first residual input boundary image to the first image processor,
the first image processor processes the first sub input image by referring to the first residual input boundary image supplied from the second image processor, and
the second image processor processes the first residual input image by referring to the first sub input boundary image supplied from the first image processor,
wherein, in the second entire input image,
a boundary of the second sub input image that is adjacent to the second residual input image is set as a second sub input boundary image, and
a boundary of the second residual input image that is adjacent to the second sub input image is set as a second residual input boundary image, and
wherein, in a case where the image processing apparatus processes the second entire input image,
the first image processor supplies the second sub input boundary image to the second image processor,
the second image processor supplies the second residual input boundary image to the first image processor,
the first image processor processes the second sub input image by referring to the second residual input boundary image supplied from the second image processor, and
the second image processor processes the second residual input image by referring to the second sub input boundary image supplied from the first image processor,

3 . The image processing apparatus according to claim 1 ,
wherein, in a case where the image processing apparatus processes the first entire input image,
the first image processor supplies the first sub input image to the second image processor,
the second image processor supplies the first residual input image to the first image processor,
the first image processor processes the first sub input image by referring to the first residual input image supplied from the second image processor, and
the second image processor processes the first residual input image by referring to the first sub input image supplied from the first image processor, and
wherein, in a case where the image processing apparatus processes the second entire input image,
the first image processor supplies the second sub input image to the second image processor,
the second image processor supplies the second residual input image to the first image processor,
the first image processor processes the second sub input image by referring to the second residual input image supplied from the second image processor, and
the second image processor processes the second residual input image by referring to the second sub input image supplied from the first image processor.

4 . The image processing apparatus according to claim 3 ,
wherein the first image processor acquires an OSD image from outside, and wherein the first image processor supplies the OSD image to the second image processor.

5 . A display apparatus comprising:
the image processing apparatus according to claim 1 ; a display.

6 . An image processing apparatus comprising:
a first image processor; and a second image processor, wherein a first entire input image is constituted by four first-unit input images, wherein a second entire input image is constituted by four second-unit input images, wherein the image processing apparatus processes one of the first entire input e and the second entire input image, wherein the first entire input image and the second entire input image are input to the first image processor and the d image processor according to any one of following (input mode 1) and (input mode 2), (input mode 1):
the four first-unit input images are input to the first image processor, and
the four second-unit input images are input to the second image processor,
(input mode 2):
three of the first-unit input images and one of the second-unit input images are input to the first image processor, and
one of the first-unit input images and three of the second-unit input images, which are not input to the first image processor, are input to the second image processor;
wherein, in a case where the image processing apparatus processes the first entire input image,
the first image processor (i) processes one or more predetermined first-unit input images among three or more first-unit input images which are input to the first image processor, and (ii) supplies remaining first-unit input images excluding the one or more predetermined first-unit input images, to the second image processor, and
the second image processor processes at least one of (i) the one of the first-unit input images which is not input to the first image processor and (ii) the remaining first-unit input images supplied from the first image processor, and
wherein, in a case where the image processing apparatus processes the second entire input image,
the second image processor (i) processes one or more predetermined second-unit input images among three or more second-unit input images which are input to the second image processor, and (ii) supplies remaining second-unit input images excluding the one or more predetermined second-unit input images, to the first image processor, and
the first image processor processes at least one of (i) the one of the second-unit input images which is not input to the second image processor and (ii) the remaining second-unit input images supplied from the second image processor.

7 . The image processing apparatus according to claim 6 ,
wherein the first entire input image and the second entire input image are input to the first image processor and the second image processor according to the (input mode 1), wherein, in a case where the image processing apparatus processes the first entire input image,
the first image processor (i) processes two predetermined first-unit input images among the four first-unit input images which are input to the first image processor, and (ii) supplies two remaining first-unit input images excluding the two predetermined first-unit input images, to the second im

Assignees

• Sharp Kk

Inventors

• Nakamura Tatsunori

Classifications

• G09G2360/06

  Use of more than one graphics processor to process data before displaying to one or more screens · CPC title

• G09G2310/0232

  Special driving of display border areas · CPC title

• G09G5/397 Primary

  Arrangements specially adapted for transferring the contents of two or more bit-mapped memories to the screen simultaneously, e.g. for mixing or overlay (G09G5/02 takes precedence) · CPC title

• G09G5/363

  Graphics controllers · CPC title

• G09G2360/122

  Tiling · CPC title