Secondary battery protection circuit and secondary battery anomaly detection system

Patent metadata

Field	Value
Publication number	US-2021126473-A1
Application number	US-201917258957-A
Country	US
Kind code	A1
Filing date	Jun 27, 2019
Priority date	Jul 10, 2018
Publication date	Apr 29, 2021
Grant date	—

Abstract

Safety is secured in such a manner that an anomaly of a secondary battery is detected with a protection circuit, for example, a phenomenon that lowers the safety of a secondary battery, particularly a micro short circuit, is detected early, and users are warned or the use of the secondary battery is stopped. A secondary battery protection circuit includes a first memory circuit electrically connected to a secondary battery, a comparison circuit electrically connected to the first memory circuit, a second memory circuit electrically connected to the comparison circuit, and a power-off switch electrically connected to the second memory circuit. The power-off switch is electrically connected to the secondary battery, and the first memory circuit includes a first transistor including an oxide semiconductor and retains a voltage value of the secondary battery in an analog manner.

First claim

1 - 11 . (canceled)

12 . A secondary battery protection circuit comprising:
a first memory circuit electrically connected to a secondary battery; a comparison circuit electrically connected to the first memory circuit; a second memory circuit electrically connected to the comparison circuit; and a power-off switch electrically connected to the second memory circuit, wherein the power-off switch is electrically connected to the secondary battery, wherein the first memory circuit comprises a first transistor comprising an oxide semiconductor, and wherein the first transistor is configured to retain a voltage value of the secondary battery in an analog manner.

13 . The secondary battery protection circuit according to claim 12 ,
wherein the second memory circuit comprises a second transistor comprising an oxide semiconductor, and wherein the second transistor is configured to retain data of the power-off switch.

14 . The secondary battery protection circuit according to claim 12 ,
wherein the comparison circuit is electrically connected to the secondary battery, and when a voltage drop of the secondary battery occurs, an output signal of the comparison circuit is inverted, an anomaly is detected, and the power-off switch is brought into an off state.

15 . The secondary battery protection circuit according to claim 12 ,
wherein the first memory circuit is subjected to writing every period Δt and the comparison circuit compares a voltage value of the secondary battery and a value retained in the first memory circuit.

16 . The secondary battery protection circuit according to claim 12 ,
wherein the first memory circuit retains an offset voltage value of a secondary battery.

17 . The secondary battery protection circuit accord according to claim 12 ,
wherein the oxide semiconductor comprises any one of indium, gallium, and zinc.

18 . A secondary battery protection circuit comprising:
a first comparison circuit electrically connected to a first memory circuit; a second memory circuit electrically connected to the secondary battery; a second comparison circuit electrically connected to the second memory circuit; and an OR circuit to which an output of the first comparison circuit and an output of the second comparison circuit are each input, wherein the first memory circuit comprises a first transistor comprising an oxide semiconductor, wherein the first transistor is configured to retain a voltage value of the secondary battery in an analog manner, wherein the second memory circuit comprises a second transistor comprising an oxide semiconductor, and wherein the second transistor is configured to retain a voltage value of the secondary battery in an analog manner with a timing different from that of the first memory circuit.

19 . The secondary battery protection circuit according to claim 18 ,
wherein the first memory circuit retains an offset voltage value of a secondary battery.

20 . The secondary battery protection circuit according to claim 18 ,
wherein the oxide semiconductor includes any one of indium, gallium, and zinc.

21 . A secondary battery anomaly detection system comprising:
a data acquisition circuit of a voltage value of a secondary battery; and a memory circuit which retains an offset voltage value of the secondary battery, wherein a warning of an anomaly is given to a user at a point in time when the voltage value of the secondary battery becomes largely different from the offset voltage value of the secondary battery.

22 . The secondary battery anomaly detection system according to claim 21 , wherein the memory circuit comprises a transistor comprising an oxide semiconductor.

23 . A secondary battery anomaly detection system comprising:
a data acquisition circuit of a voltage value of a secondary battery; and a memory circuit which retains an offset voltage value of the secondary battery, wherein charging stops at a point in time when the voltage value of the secondary battery becomes largely different from the offset voltage value of the secondary battery.

24 . The secondary battery anomaly detection system according to claim 23 , wherein the memory circuit comprises a transistor comprising an oxide semiconductor.

25 . A secondary battery anomaly detection system comprising:
a data acquisition circuit of a voltage value of a secondary battery; and a memory circuit which retains an offset voltage value of the secondary battery, wherein a charging condition is changed in accordance with the number of times or the strength of an anomaly point where the voltage value of the secondary battery becomes largely different from the offset voltage value of the secondary battery.

26 . The secondary battery anomaly detection system according to claim 25 , wherein the memory circuit comprises a transistor comprising an oxide semiconductor.

Assignees

• Semiconductor Energy Lab

Inventors

• Ikeda Takayuki
• Kozuma Munehiro
• Matsuzaki Takanori
• Tajima Ryota
• Yamazaki Shunpei
• Okamoto Yuki

Classifications

• H02J7/685

  using connection detecting circuits (H02J7/68 takes precedence) · CPC title

• H02J7/663 Primary

  using battery or load disconnect circuits (H02J9/002 takes precedence) · CPC title

• H02J7/825

  Detection of fully charged condition · CPC title

• H02J7/61 Primary

  against overcharge · CPC title

• H01M50/574

  Devices or arrangements for the interruption of current · CPC title