Power stage package including flexible circuit and stacked die

Patent metadata

Field	Value
Publication number	US-2021111105-A1
Application number	US-201916597808-A
Country	US
Kind code	A1
Filing date	Oct 9, 2019
Priority date	Oct 9, 2019
Publication date	Apr 15, 2021
Grant date	—

Abstract

A semiconductor package includes a substrate, a set of terminals protruding from a first surface of the substrate, a power stage physically and thermally coupled to the first surface of the substrate, and a flexible circuit including at least one circuit layer forming power stage conductors and control circuit conductors disposed on a flexible insulating substrate layer. The power stage is between the flexible circuit and the substrate and is mounted on a first surface of the flexible circuit such that the power stage is electrically connected to the power stage conductors. The package includes a die mounted on a second surface of the flexible circuit opposite the power stage. An output of the die is electrically connected to an input of the power stage via the control circuit conductors.

First claim

What is claimed is:

1 . A semiconductor package comprising:
a substrate forming a first surface and a second surface that opposes the first surface; a set of terminals protruding from the first surface of the substrate; a power stage physically and thermally coupled to the first surface of the substrate; a flexible circuit including at least one circuit layer forming power stage conductors and control circuit conductors disposed on a flexible insulating substrate layer, wherein the power stage is mounted on a first surface of the flexible circuit such that the power stage is electrically connected to the power stage conductors, wherein the flexible circuit is opposite the substrate relative the power stage such that the power stage is between the flexible circuit and the substrate; and a die mounted on a second surface of the flexible circuit opposite the power stage such that the die is electrically connected to the control circuit conductors, wherein an output of the die is electrically connected to an input of the power stage via the control circuit conductors.

2 . The semiconductor package of claim 1 , wherein the flexible circuit forms alignment features engaged with the set of terminals protruding from the substrate.

3 . The semiconductor package of claim 1 , wherein a grounded portion of the power stage conductors is electrically connected to a grounded portion of the control circuit conductors via a ground pin of the set of terminals.

4 . The semiconductor package of claim 3 , wherein the grounded portion of the power stage conductors, the ground pin and the grounded portion of the control circuit conductors provides a ground return path for an electrical signal between the input of the power stage and the output of the die.

5 . The semiconductor package of claim 1 , wherein the output of the die is electrically connected to the input for the power stage via the control circuit conductors and one of the set of terminals.

6 . The semiconductor package of claim 1 ,
wherein the power stage is a first power stage, the semiconductor package further comprising a second power stage physically and thermally coupled to the first surface of the substrate such that the second power stage is between the flexible circuit and the substrate, wherein the first power stage is electrically connected to the second power stage via the power stage conductors.

7 . The semiconductor package of claim 1 , wherein the insulating substrate layer of the flexible circuit is a first insulating substrate layer, the flexible circuit further including a second insulating substrate layer on an opposite side of the power stage conductors relative to the first insulating substrate layer.

8 . The semiconductor package of claim 1 , wherein the control circuit conductors are on an outer surface of the flexible circuit.

9 . The semiconductor package of claim 1 , further comprising a thermal interface material between the power stage and the first surface of the substrate.

10 . The semiconductor package of claim 1 , further comprising:
a first set of solder bumps forming electrical connections between the power stage and the flexible circuit such that the die is mounted on the first surface of the flexible circuit in a first flipchip arrangement; and a second set of solder bumps between the die and the flexible circuit such that the power stage is mounted on the second surface of the flexible circuit in a second flipchip arrangement.

11 . The semiconductor package of claim 1 , further comprising one or more passive components of a sensing circuit mounted on the second surface of the flexible circuit and electrically connected to the die via the control circuit conductors.

12 . The semiconductor package of claim 1 , further comprising mold compound at least partially covering the power stage, the die, the flexible circuit and the substrate with the second surface of the substrate exposed.

13 . The semiconductor package of claim 1 , further comprising a heat sink physically and thermally coupled to a second surface of the substrate, the second surface of the substrate opposing the first surface of the substrate.

14 . The semiconductor package of claim 1 , wherein the power stage includes at least one a group consisting of:
a field effect transistor (FET); a junction FET (JFET); a metal-oxide-semiconductor field-effect transistor (MOSFET); a metal-semiconductor field-effect transistor (MESFET); an insulated-gate bipolar transistor (IGBT); a bipolar junction transistor (BJT); a thyristor; an integrated gate commutated thyristor (IGCT); a silicon controlled rectified (SCR); a triode for alternating current (TRIAC); a high electron mobility transistor (HEMT); and a uni junction transistor (UJT).

15 . The semiconductor package of claim 1 , wherein a voltage rating of the power stage is at least 80 volts.

16 . The semiconductor package of claim 1 , wherein the die comprises a semiconductor die.

17 . The semiconductor package of claim 1 , further comprising a gallium nitride die that includes the power stage.

18 . A method of forming a package comprising:
physically and thermally coupling a power stage to a first surface of a substrate to form a first subassembly, the substrate forming the first surface and a second surface that opposes the first surface, wherein a set of terminals protrude from the first surface of the substrate; mounting a die on a first surface of a flexible circuit such that the die is electrically connected to a control circuit conductors of the flexible circuit to form a second subassembly, the flexible circuit including at least one circuit layer forming power stage conductors and control circuit conductors disposed on a flexible insulating substrate layer, the flexible circuit forming the first surface and a second surface that opposes the first surface of the flexible circuit; aligning alignment features of the flexible circuit of the second subassembly with the set of terminals of first assembly to locate electrical contacts of the power stage with electrical contact surfaces of the power stage conductors on the second surface of the flexible circuit; and electrically connecting the electrical contacts of the power stage with the electrical contact surfaces of the power stage conductors to electrically connect the power stage of the first subassembly to the power stage conductors of the second subassembly.

19 . The method of claim 18 ,
wherein mounting the die on the second surface of the flexible circuit includes reflow processing a first set of solder bumps to form electrical connections between the control circuit conductors of the flexible circuit and the die, and wherein electrically connecting the electrical contacts of the power stage with the electrical contact surfaces of the power stage conductors includes reflow processing a second set of solder bumps to form electrical connections between the power stage conductors of the flexible circuit and the power stage.

20 . The method of claim 18 , further comprising covering portions of the die, the power stage, and the flexible circuit with mold compound, leaving the second surface of the substrate exposed.

21 . A semiconductor package comprising:
a substrate forming a first surface of the substrate, and a second surface of the substrate, the second surface of the substrate opposing the first surface of the substrate; a set of terminals protruding from the first surface of the

Assignees

• Texas Instruments Inc

Inventors

• Kim Woochan
• Arora Vivek Kishorechand

Classifications

• H10W90/00

  Package configurations · CPC title

• H10W72/50

  Bond wires · CPC title

• H10W70/688

  Flexible insulating substrates · CPC title

• H10W70/685

  comprising multiple insulating layers · CPC title

• H10W70/635

  Through-vias · CPC title