Multi-State Programming for Memory Devices

Patent metadata

Field	Value
Publication number	US-2021104275-A1
Application number	US-202017127290-A
Country	US
Kind code	A1
Filing date	Dec 18, 2020
Priority date	Dec 14, 2018
Publication date	Apr 8, 2021
Grant date	—

Abstract

Storage device programming methods, systems and media are described. A method may include encoding data to generate an encoded set of data. A first programming operation may write the encoded set of data to a memory device. The method includes encoding, using a second encoding operation based on the data, to generate a second set of encoded data. The second set of encoded data is stored to a cache. A first decoding operation is performed, based on the second set of encoded data and the encoded set of data, to generate a decoded set of data. A second decoding operation is performed to generate a second decoded set of data. The second decoded set of data is encoded to generate a third set of encoded data. The method includes performing a second programming operation to write the third set of encoded data to the memory device.

First claim

1 - 20 . (canceled)

21 . A method for programming a memory device, comprising:
executing a first encoding operation to generate a first set of encoded data; performing a first programming operation to store the first set of encoded data into the memory device; executing, based on the first set of encoded data, a second encoding operation to generate a second set of encoded data; executing one or more decoding operations based on the first set of encoded data stored in the memory device and the second set of encoded data, to generate a set of decoded data; executing, based on the set of decoded data, an encoding operation to generate a third set of encoded data; and performing a second programming operation to store the third set of encoded data to the same memory device.

22 . The method of claim 21 , wherein an amount of the second set of encoded data is less than an amount of the first set of encoded data.

23 . The method of claim 21 , comprising:
prior to executing the one or more decoding operations, storing the second set of encoded data to a memory.

24 . The method of claim 23 , wherein the memory is different from the memory device.

25 . The method of claim 21 , wherein executing the one or more decoding operations comprises:
performing a first decoding operation, based on the first set of encoded data from the memory device and the second set of encoded data, to generate a first set of decoded data; and performing a second decoding operation, based on the first set of decoded data, to generate the set of decoded data.

26 . The method of claim 23 , wherein the second set of encoded data stored in the memory comprises additional parity bits for an error-correcting code, and the third set of encoded data comprises the same data as the first set of encoded data.

27 . The method of claim 21 , wherein the first programming operation comprises a foggy programming operation, and wherein the second programming operation comprises a fine programming operation.

28 . The method of claim 21 , wherein the one or more decoding operations comprise a foggy decoding operation and an error-correcting code decoding operation.

29 . The method of claim 21 , comprising:
generating an additional page of data based on an XOR operation of a number of bits of data in each cell of the memory device.

30 . The method of claim 21 , wherein the first set of encoded data comprises four pages of data, and the second set of encoded data comprises one page of data, and the set of decoded data comprises four pages of data.

31 . The method of claim 21 , comprising:
receiving host data from a host device, wherein executing the first encoding operation comprises generating, using an error-correcting code encoding scheme, the first set of encoded data based on the host data, and wherein executing the second encoding operation comprises providing the first set of encoded data to a foggy encoder for performing a foggy encoding operation to generate the second set of encoded data.

32 . A system, comprising:
a memory device; and one or more controllers configured to cause:
executing a first encoding operation to generate a first set of encoded data;
performing a first programming operation to store the first set of encoded data into the memory device;
executing, based on the first set of encoded data, a second encoding operation to generate a second set of encoded data;
executing one or more decoding operations based on the first set of encoded data stored in the memory device and the second set of encoded data, to generate a set of decoded data;
executing, based on the set of decoded data, an encoding operation to generate a third set of encoded data; and
performing a second programming operation to store the third set of encoded data to the memory device.

33 . The system of claim 32 , wherein an amount of the second set of encoded data is less than an amount of the first set of encoded data.

34 . The system of claim 32 , wherein the one or more controllers are configured to cause:
prior to executing the one or more decoding operations, storing the second set of encoded data to a memory.

35 . The system of claim 34 , wherein the memory is different from the memory device.

36 . The system of claim 32 , wherein executing the one or more decoding operations comprises:
performing a first decoding operation, based on the first set of encoded data from the memory device and the second set of encoded data, to generate a first set of decoded data; and performing a second decoding operation, based on the first set of decoded data, to generate the set of decoded data.

37 . The system of claim 32 , wherein the one or more controllers are configured to cause:
receiving host data from a host device, wherein executing the first encoding operation comprises generating, using an error-correcting code encoding scheme, the first set of encoded data based on the host data, and wherein executing the second encoding operation comprises providing the first set of encoded data to a foggy encoder for performing a foggy encoding operation to generate the second set of encoded data.

38 . An apparatus, comprising:
means for executing a first encoding operation to generate a first set of encoded data; means for performing a first programming operation to store the first set of encoded data into a memory device; means for executing, based on the first set of encoded data, a second encoding operation to generate a second set of encoded data; means for executing one or more decoding operations based on the first set of encoded data stored in the memory device and the second set of encoded data, to generate a set of decoded data; means for executing, based on the set of decoded data, an encoding operation to generate a third set of encoded data; and means for performing a second programming operation to store the third set of encoded data to the memory device.

39 . The apparatus of claim 38 , wherein an amount of the second set of encoded data is less than an amount of the first set of encoded data.

40 . The apparatus of claim 39 , comprising:
means for receiving host data from a host device, wherein the means for executing the first encoding operation comprises means for generating, using an error-correcting code encoding scheme, the first set of encoded data based on the host data, and wherein the means for executing the second encoding operation comprises means for executing a foggy encoding operation to generate the second set of encoded data.

Assignees

• Western Digital Tech Inc

Inventors

• Barndt Richard David
• Rub Bernardo
• El Gamal Mostafa

Classifications

• G11C29/781

  combined in a redundant decoder · CPC title

• G11C11/5642

  Sensing or reading circuits; Data output circuits · CPC title

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title

• G11C11/5628 Primary

  Programming or writing circuits; Data input circuits · CPC title

• G11C2211/5623

  Concurrent multilevel programming and reading · CPC title