Analog to digital converter device and noise shaping digital slope analog to digital converter circuitry

Patent metadata

Field	Value
Publication number	US-2021099183-A1
Application number	US-202016848133-A
Country	US
Kind code	A1
Filing date	Apr 14, 2020
Priority date	Sep 27, 2019
Publication date	Apr 1, 2021
Grant date	—

Abstract

An analog-to-digital converter (ADC) device includes an ADC circuitry and a digital slope ADC circuitry. The ADC circuitry is configured to generate first bits and a first voltage according to an input signal. The digital slope ADC circuitry is configured to generate a second voltage at a node according to the first voltage and to gradually adjust the second voltage to generate second bits. After the second bits are generated, the digital slope ADC circuitry is further configured to perform a noise shaping function according to a first residual signal of the node.

First claim

What is claimed is:

1 . An analog-to-digital converter (ADC) device, comprising:
an ADC circuitry configured to generate a plurality of first bits and a first voltage according to an input signal; and a digital slope ADC circuitry configured to generate a second voltage at a node according to the first voltage and to gradually adjust the second voltage to generate a plurality of second bits, wherein after the plurality of second bits are generated, the digital slope ADC circuitry is further configured to perform a noise shaping function according to a first residual signal of the node.

2 . The ADC device of claim 1 , wherein the digital slope ADC circuitry comprises:
a slope generator circuit configured to receive the first voltage according to a clock signal, and to output the second voltage to the node according to the first voltage, a reference voltage, and a plurality of switching signals; a delay line circuit configured to generate the plurality of switching signals and a plurality of third bits according to an enable signal and a valid signal; an encoder circuit configured to generate the plurality of second bits according to the plurality of third bits; and a comparator circuit configured to compare the second voltage with a predetermined voltage, in order to generate the valid signal.

3 . The ADC device of claim 2 , wherein the slope generator circuit comprises:
a capacitor array comprising a plurality of first capacitors and a second capacitor, wherein first terminals of the plurality of first capacitors are coupled to the node and are configured to receive the first voltage according to the clock signal, in order to store the received first voltage as the second voltage, second terminals of the plurality of first capacitors receive a plurality of control signals respectively, and the second capacitor is coupled to the node to store the first residue signal; and a switching circuit configured to generate the plurality of control signals according to the plurality of switching signals.

4 . The ADC device of claim 2 , wherein the delay line circuit comprises:
a logic gate configured to generate a first switching signal of the plurality of switching signals according to the enable signal and the valid signal; a plurality of delay cells coupled in series and configured to generate remaining switching signals of the plurality of the switching signals according to the first switching signal; a plurality of flip flops configured to be triggered by the valid signal, in order to output the plurality of switching signals as the plurality of third bits respectively; and a logic control circuit configured to calibrate the second voltage before the noise shaping function is performed.

5 . The ADC device of claim 4 , wherein the slope generator circuit comprises a capacitor array, the capacitor array is configured to store the first voltage as the second voltage, and before the noise shaping function is performed, the logic control circuit is configured to reset at least one capacitor of the capacitor array, in order to calibrate the second voltage.

6 . The ADC device of claim 4 , wherein the slope generator circuit comprises a compensation capacitor, and before the noise shaping function is performed, the logic control circuit is configured to output an adjustment voltage to the compensation capacitor, in order to calibrate the second voltage.

7 . The ADC device of claim 2 , wherein the enable signal is to indicate that the digital slope ADC circuitry starts performing an analog-to-digital conversion.

8 . The ADC device of claim 2 , wherein the valid signal is to indicate that the digital slope ADC circuitry finishes performing an analog-to-digital conversion.

9 . The ADC device of claim 2 , wherein the comparator circuit is configured to compare the second voltage with the predetermined voltage, in order to detect a zero crossing point of the second voltage.

10 . The ADC device of claim 1 , wherein the digital slope ADC circuitry comprises:
a comparator circuit configured to detect a zero crossing point of the second voltage, in order to generate the plurality of second bits; and a noise shaping circuit configured to output a second residue signal to the comparator circuit according to the first residue signal, in order to perform the noise shaping function.

11 . The ADC device of claim 10 , wherein the noise shaping circuit comprises:
a first capacitor; a first switch coupled to the node and configured to be turned on according to a first control signal, in order transfer the first residue signal to the first capacitor; a second capacitor coupled to the first switch and the comparator circuit; and a second switch configured to be turned on according to a second control signal to couple the first capacitor the second capacitor, in order to generate the second residue signal.

12 . A digital slope ADC circuitry, comprising:
a slope generator circuit configured to output a voltage at a node according to a clock signal and an input signal; a delay line circuit configured to generate a plurality of first bits according an enable signal and a valid signal and to generate a plurality of switching signals to the slope generator circuit, in order to gradually adjust the voltage; a comparator circuit configured to detect a zero crossing point of the voltage, in order to generate the valid signal; and a noise shaping circuit configured to output a second residue signal to the comparator circuit according to a first residue signal of the node after the plurality of first bits are generated, in order to perform a noise shaping function.

13 . The digital slope ADC circuitry of claim 12 , wherein the slope generator circuit comprises a capacitor array, the delay line circuit comprises a logic control circuit, the capacitor array is configured to store the voltage, and the logic control circuit is configured to reset at least one capacitor of the capacitor array before the noise shaping function is performed, in order to calibrate the voltage.

14 . The digital slope ADC circuitry of claim 12 , wherein the slope generator circuit comprises:
a capacitor array, comprising a plurality of first capacitors and a second capacitor, wherein first terminals of the plurality of first capacitors are coupled to the node and are configured to store the voltage according to the clock signal and the input signal, second terminals of the plurality of first capacitors are configured to receive a plurality of control signals respectively, and the second capacitor is coupled to the node to store the first residue signal; and a switching circuit configured to generate the plurality of control signals according to the switching signals.

15 . The digital slope ADC circuitry of claim 12 , wherein the delay line circuit comprises:
a logic gate configured to generate a first switching signal of the plurality of switching signals according to the enable signal and the valid signal; a plurality of delay cells coupled in series and configured to generate remaining switching signals of the plurality of the switching signals according to the first switching signal; a plurality of flip flops configured to be triggered by the valid signal, in order to output the plurality of switching signals as the plurality of first bits respectively; and a logic control circuit configured to calibrate the voltage before the noise shaping function is performed.

16 . The digital slope ADC circuitry of claim 15 , further comprising:
an encoder circuit configured to generate a plurality of second

Assignees

• Realtek Semiconductor Corp

Inventors

• Lai Jie-Fan
• Huang Shih-Hsiung
• Chen Yu-Chang
• Chen Chih-Lung
• Hung Tzu-Hao
• Lee Tai-Cheng

Classifications

• H03M1/804

  with charge redistribution · CPC title

• H03M1/56

  Input signal compared with linear ramp · CPC title

• H03M1/145 Primary

  the steps being performed sequentially in series-connected stages (H03M1/141, H03M1/143, H03M1/16 take precedence) · CPC title

• H03M1/1009

  Calibration · CPC title

• H03M1/08 Primary

  of noise {(H03M1/0617 takes precedence)} · CPC title