Semiconductor Devices Including Resistor Structures

Patent metadata

Field	Value
Publication number	US-2021098563-A1
Application number	US-202017118078-A
Country	US
Kind code	A1
Filing date	Dec 10, 2020
Priority date	Jun 26, 2017
Publication date	Apr 1, 2021
Grant date	—

Abstract

A semiconductor device is provided including a resistor structure, the semiconductor device including a substrate having an upper surface perpendicular to a first direction; a resistor structure including a first insulating layer on the substrate, a resistor layer on the first insulating layer, and a second insulating layer on the resistor layer; and a resistor contact penetrating the second insulating layer and the resistor layer. The tilt angle of a side wall of the resistor contact with respect to the first direction varies according to a height from the substrate. The semiconductor device has a low contact resistance and a narrow variation of contact resistance.

First claim

1 - 20 . (canceled)

21 . A semiconductor device comprising:
a substrate including a first region and a second region; a first device isolation layer disposed on the first region of the substrate and the second region of the substrate; a second device isolation layer disposed on the first region of the substrate and the second region of the substrate; an active region disposed on the first region of the substrate and the second region of the substrate, and disposed between the first device isolation layer and the second device isolation layer; a first gate disposed on the first device isolation layer, the second device isolation layer, and the active region; a second gate disposed on the first device isolation layer, the second device isolation layer, and the active region; a third gate disposed on the first device isolation layer, the second device isolation layer, and the active region; a fourth gate disposed on the first device isolation layer, the second device isolation layer, and the active region; an epitaxial source/drain disposed on the active region; a first insulation layer disposed between the first gate and the second gate; a second insulation layer disposed between the third gate and the fourth gate; a resistor structure disposed on the third gate, the fourth gate, and the second insulation layer; a source/drain contact contacting the epitaxial source/drain; a gate contact contacting the first gate; and a resistor contact contacting the resistor structure, wherein: each of the first gate and the second gate is disposed on the first region of the substrate, each of the third gate and the fourth gate is disposed on the second region of the substrate, the epitaxial source/drain is disposed on the first region of the substrate, and the resistor structure is disposed on the second region of the substrate.

22 . The semiconductor device of claim 21 , wherein no epitaxial source/drain is disposed on the second region of the substrate.

23 . The semiconductor device of claim 21 , wherein the epitaxial source/drain is disposed between the first gate and the second gate.

24 . The semiconductor device of claim 21 , wherein the resistor contact vertically overlaps the active region, and vertically overlaps the second insulation layer.

25 . The semiconductor device of claim 21 , wherein:
the source/drain contact is disposed on the epitaxial source/drain, the gate contact is disposed on the first gate, and the resistor contact is disposed on the resistor structure.

26 . The semiconductor device of claim 21 , wherein:
a bottom surface of the source/drain contact is disposed lower than a top surface of the epitaxial source/drain, a bottom surface of the gate contact is disposed lower than a top surface of the first gate, and a bottom surface of the resistor contact is disposed lower than a top surface of the resistor structure.

27 . The semiconductor device of claim 21 , wherein a bottom surface of the source/drain contact is disposed lower than a bottom surface of the resistor contact.

28 . The semiconductor device of claim 21 , wherein the resistor contact penetrates the resistor structure such that a bottom surface of the resistor contact is disposed lower than a bottom surface of the resistor structure.

29 . The semiconductor device of claim 21 , wherein a bottom surface of the resistor contact is disposed higher than a bottom surface of the resistor structure.

30 . The semiconductor device of claim 21 , wherein a width of an upper portion of the resistor contact is greater than a width of a lower portion of the resistor contact.

31 . The semiconductor device of claim 21 , wherein a top surface of the resistor contact is circular.

32 . The semiconductor device of claim 21 , wherein a top surface of the resistor contact is oval.

33 . A semiconductor device comprising:
a substrate including a first region and a second region; a first device isolation layer disposed on the first region of the substrate and the second region of the substrate; a second device isolation layer disposed on the first region of the substrate and the second region of the substrate; an active region disposed on the first region of the substrate and the second region of the substrate, and disposed between the first device isolation layer and the second device isolation layer; a first gate disposed on the first device isolation layer, the second device isolation layer, and the active region; a second gate disposed on the first device isolation layer, the second device isolation layer, and the active region; a third gate disposed on the first device isolation layer, the second device isolation layer, and the active region; a fourth gate disposed on the first device isolation layer, the second device isolation layer, and the active region; a first epitaxial source/drain disposed on the active region; a second epitaxial source/drain disposed on the active region; a first insulation layer disposed between the first gate and the second gate; a second insulation layer disposed between the third gate and the fourth gate; a resistor structure disposed on the second insulation layer; a first source/drain contact contacting the first epitaxial source/drain; a gate contact contacting the first gate; and a resistor contact contacting the resistor structure, wherein: each of the first gate and the second gate is disposed on the first region of the substrate, each of the third gate and the fourth gate is disposed on the second region of the substrate, the first epitaxial source/drain disposed on the first region of the substrate, the second epitaxial source/drain disposed on the second region of the substrate, the resistor structure is disposed on the second region of the substrate, and the resistor contact penetrates the resistor structure and contacts the second insulation layer.

34 . The semiconductor device of claim 33 , wherein the resistor structure is disposed on the third gate and the fourth gate.

35 . The semiconductor device of claim 33 , wherein no resistor structure is disposed on the first region of the substrate.

36 . The semiconductor device of claim 33 , wherein a width of an upper portion of the resistor contact is greater than a width of a lower portion of the resistor contact.

37 . A semiconductor device comprising:
a substrate including a first region and a second region; a first device isolation layer disposed on the first region of the substrate; a second device isolation layer disposed on the first region of the substrate; an active region disposed on the first region of the substrate, and disposed between the first device isolation layer and the second device isolation layer; a first gate disposed on the first device isolation layer, the second device isolation layer, and the active region; a second gate disposed on the first device isolation layer, the second device isolation layer, and the active region; a third gate disposed on the second region of the substrate; a fourth gate disposed on the second region of the substrate; a first epitaxial source/drain disposed on the active region; a first insulation layer disposed between the first gate and the second gate; a second insulation layer disposed between the third gate and the fourth gate; a resistor structure disposed on the third gate, the fourth gate, and the second insulation layer; a source/drain contact contacting the first epitaxial source/drain; a gate contact contacting the first gate; and a resistor

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Tae-Yeol
• Ra Hyon-Wook
• Lee Seo-Bum
• Kim Jun-Soo
• Shin Chung-Hwan

Classifications

• H10D64/0112

  using conductive layers comprising silicides · CPC title

• H10W20/425

  Barrier, adhesion or liner layers · CPC title

• H10W20/077

  on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence) · CPC title

• H10W20/48

  Insulating materials thereof · CPC title

• H10W20/43

  Layouts of interconnections · CPC title