Non-volatile multi-level cell memory using a ferroelectric superlattice and related systems

Patent metadata

Field	Value
Publication number	US-2021098060-A1
Application number	US-202017032847-A
Country	US
Kind code	A1
Filing date	Sep 25, 2020
Priority date	Sep 26, 2019
Publication date	Apr 1, 2021
Grant date	—

Abstract

An N-bit non-volatile multi-level memory cell (MLC) can include a lower electrode and an upper electrode spaced above the lower electrode. N ferroelectric material layers can be vertically spaced apart from one another between the lower electrode and the upper electrode, wherein N is at least 2 and at least one dielectric material layer having a thickness of less than 20 nm can be located between the N ferroelectric material layers.

First claim

What is claimed:

1 . An N-bit non-volatile multi-level memory cell (MLC) comprising:
a lower electrode; an upper electrode spaced above the lower electrode; N ferroelectric material layers vertically spaced apart from one another between the lower electrode and the upper electrode, wherein N is at least 2; and at least one dielectric material layer having a thickness of less than 20 nm located between the N ferroelectric material layers.

2 . The N-bit non-volatile multi-level memory cell of claim 1 wherein N is equal to 2 providing a first ferroelectric material layer and a second ferroelectric material layer and the at least one dielectric material layer has a thickness of about 1 nm.

3 . The N-bit non-volatile multi-level memory cell of claim 2 wherein the first ferroelectric material layer and a second ferroelectric material layer comprise ZrO 2 .

4 . The N-bit non-volatile multi-level memory cell of claim 3 wherein the first ferroelectric material layer has a thickness of the about 1 nm and a second ferroelectric material layer has a thickness of about 1 nm.

5 . The N-bit non-volatile multi-level memory cell of claim 2 wherein the first ferroelectric material layer comprises HfO 2 and the second ferroelectric material layer comprises HfO 2 .

6 . The N-bit non-volatile multi-level memory cell of claim 1 wherein N is equal to 2 providing a first ferroelectric material layer and a second ferroelectric material layer and the at least one dielectric material layer has a thickness of about 5 nm.

7 . The N-bit non-volatile multi-level memory cell of claim 6 wherein the first ferroelectric material layer and a second ferroelectric material layer comprise ZrO 2 and are located on opposite surfaces of the at least one dielectric material layer.

8 . The N-bit non-volatile multi-level memory cell of claim 7 wherein the first ferroelectric material layer has a thickness of the about 1 nm and a second ferroelectric material layer has a thickness of about 1 nm.

9 . The N-bit non-volatile multi-level memory cell of claim 6 wherein the first ferroelectric material layer comprises HfO 2 and the second ferroelectric material layer comprises HfO 2 .

10 . The N-bit non-volatile multi-level memory cell of claim 1 wherein N ferroelectric material layers comprise a first ferroelectric material layer and a second ferroelectric material layer, the N-bit non-volatile multi-level memory cell further comprising:
a first dielectric material layer between the upper electrode and the first ferroelectric material layer;
a second dielectric material layer between the first ferroelectric material layer and the second ferroelectric material layer; and
a third dielectric material layer between the lower electrode and the second ferroelectric material layer.

11 . The N-bit non-volatile multi-level memory cell of claim 10 wherein:
the first dielectric material layer has a thickness of about 1 nm and comprises HfO 2 ;
the first ferroelectric material layer has a thickness of about 1 nm and comprises ZrO 2
the second dielectric material layer has a thickness of about 1 nm and comprises HfO 2 ;
the second ferroelectric material layer has a thickness of about 1 nm and comprises ZrO 2 ; and
the third dielectric material layer has a thickness of about 1 nm and comprises HfO 2 .

12 . The N-bit non-volatile multi-level memory cell of claim 10 wherein:
the first dielectric material layer has a thickness of about 1 nm and comprises HfO 2 ;
the first ferroelectric material layer has a thickness of about 1 nm and comprises ZrO 2
the second dielectric material layer has a thickness of about 5nm and comprises HfO 2 ;
the second ferroelectric material layer has a thickness of about 1 nm and comprises ZrO 2 ; and
the third dielectric material layer has a thickness of about 1 nm and comprises HfO 2 .

13 . The N-bit non-volatile multi-level memory cell of claim 1 further comprises:
a write pulse circuit coupled across the upper electrode and the lower electrode, the write pulse circuit configured to switch a polarization of each of the N ferroelectric material layers using a respective predefined voltage pulse.

14 . The N-bit non-volatile multi-level memory cell of claim 13 wherein the write pulse circuit is configured to write any of a state to the N-bit non-volatile multi-level memory cell using a series of voltage pulses predefined to establish a polarization for each of the N ferroelectric material layers defining the state.

15 . The N-bit non-volatile multi-level memory cell of claim 10 wherein:
the first ferroelectric material layer has a thickness in a range between about 0.5 nm and about 10 nm.

16 . The N-bit non-volatile multi-level memory cell of claim 10 wherein:
the second dielectric material layer has a thickness in a range between about 0.5 nm and about 10 nm.

17 . An N-bit non-volatile multi-level memory cell (MLC) comprising:
a lower electrode; an upper electrode spaced above the lower electrode; N ferroelectric material layers vertically spaced apart from one another between the lower electrode and the upper electrode, wherein N is at least 2; and at least one dielectric material layer located between the N ferroelectric material layers, wherein each of the N ferroelectric material layers is configured to provide a respective polarization to encode N states for the N-bit non-volatile multi-level memory cell.

18 . An N-bit non-volatile multi-level memory cell (MLC) comprising:
a lower electrode; an upper electrode spaced above the lower electrode; N ferroelectric material layers vertically spaced apart from one another between the lower electrode and the upper electrode, wherein N is at least 2; and at least one dielectric material layer located between the N ferroelectric material layers, wherein the N ferroelectric material layers provide a multi-peak E c distribution associated with each peak in the multi-peak E c distribution representing a respective data bit in the MLC.

19 . The N-bit non-volatile multi-level memory cell of claim 18 wherein the multi-peak E c distribution representing the respective data bit is fully switched during a write operation.

Assignees

• Univ California
• Univ Notre Dame Du Lac

Inventors

• Ni Kai
• Datta Suman
• Kummel Andrew

Classifications

• H10D1/692

  Electrodes · CPC title

• H10D1/68 Primary

  Capacitors having no potential barriers · CPC title

• G11C11/221

  using ferroelectric capacitors · CPC title

• G11C11/5657 Primary

  using ferroelectric storage elements · CPC title

• G11C11/2275

  Writing or programming circuits or methods · CPC title