Printed circuit board

Patent metadata

Field	Value
Publication number	US-2021090902-A1
Application number	US-202016952782-A
Country	US
Kind code	A1
Filing date	Nov 19, 2020
Priority date	Sep 29, 2017
Publication date	Mar 25, 2021
Grant date	—

Abstract

A printed circuit board according to an embodiment includes: an insulating layer; a first pad disposed on a first surface of the insulating layer; a first conductive layer disposed on the first pad and including gold (Au); a second pad disposed on a second surface of the insulating layer; and a second conductive layer disposed on the second pad and including gold (Au), wherein the first conductive layer is a conductive layer connected to a wire, the second conductive layer is a conductive layer connected to a solder, and the first conductive layer is thicker than the second conductive layer.

First claim

1 . A circuit board comprising:
an insulating layer; a first pad disposed on a first surface of the insulating layer; a first conductive layer disposed on the first pad and including gold (Au); a second pad disposed on a second surface of the insulating layer; and a second conductive layer disposed on the second pad and including gold (Au), wherein the first conductive layer includes a first region in contact with the first pad and a second region spaced apart from the first pad, wherein the first region of the first conductive layer and the second region of the first conductive layer are monolithically formed with each other, wherein the second region of the first conductive layer comprises a portion of the first conductive layer that is bent in an inward direction.

2 . The circuit board of claim 1 , wherein the second conductive layer includes a third region in contact with the second pad and a fourth region spaced apart from the second pad,
wherein the third region of the second conductive layer and the fourth region of the second conductive layer are monolithically formed with each other, wherein the fourth region of the second conductive layer comprises a portion of the second conductive layer that is bent in an inward direction.

3 . The circuit board of claim 2 , wherein the first conductive layer is connected to a wire, and
wherein the second conductive layer is connected to a solder.

4 . The circuit board of claim 1 , wherein the insulating layer includes a plurality of insulating layers,
wherein the first pad is disposed on an upper surface of a first insulating layer disposed at an uppermost portion of the plurality of insulating layers, and wherein the second pad is disposed under a lower surface of a second insulating layer disposed at a lowermost portion of the plurality of insulating layers.

5 . The circuit board of claim 2 , wherein the portion of the second region of the first conductive layer is closest to the insulating layer and is spaced apart from the first pad, and
wherein the portion of the fourth region of the second conductive layer is closest to the insulating layer and is spaced apart from the second pad.

6 . The circuit board of claim 3 , wherein each of the first pad and the second pad includes:
a plating seed layer disposed at a surface of the uppermost insulating layer or the lowermost insulating layer and including copper; a first pattern disposed on the plating seed layer and including copper; and a second pattern disposed on the first pattern and including copper.

7 . The circuit board of claim 6 , wherein the first pattern of the first pad is thicker than the second pattern of the first pad, and
wherein the first pattern of the second pad is thicker than the second pattern of the second pad.

8 . The circuit board of claim 6 , wherein a central portion of an upper surface of the first pattern of the first pad is located higher than an outer side portion of the first pattern of the first pad, and
wherein a central portion of an upper surface of the first pattern of the second pad is located higher than an outer side portion of the first pattern of the second pad.

9 . The circuit board of claim 6 , wherein a width of an upper surface of the first pattern of the first pad is larger than a width of a lower surface of the first pattern of the first pad, and
wherein a width of an upper surface of the first pattern of the second pad is larger than a width of a lower surface of the first pattern of the second pad.

10 . The circuit board of claim 6 , wherein the first region of the first conductive layer is in direct physical contact with the second pattern of the first pad and the second region of the first conductive layer extends from the first region of the first conductive layer and is spaced apart from the plating seed layer of the first pad, the first pattern of the first pad, and the second pattern of the first pad, and
wherein the second region of the first conductive layer is not in physical contact with any of the plating seed layer of the first pad, the first pattern of the first pad, and the second pattern of the first pad.

11 . The circuit board of claim 10 , wherein the third region of the second conductive layer is in direct physical contact with the second pattern of the second pad and the fourth region of the second conductive layer extends from the third region of the second conductive layer and is spaced apart from the plating seed layer of the second pad, the first pattern of the second pad, and the second pattern of the second pad, and
wherein the fourth region of the second conductive layer is not in physical contact with any of the plating seed layer of the second pad, the first pattern of the second pad, and the second pattern of the second pad.

12 . A method of manufacturing a circuit board, comprising:
forming first and second plating seed layers at an uppermost insulating layer and a lowermost insulating layer, respectively; forming a first pad and a second pad on the first and second plating seed layers, respectively; and proceeding electrolytic plating in a plating tank in which plating spaces on the surface on which the first pad is formed and on the surface on which the second pad is formed are separated to form a first conductive layer on the first pad and a second conductive layer on the second pad, wherein the first conductive layer is formed to have a thickness greater than that of the second conductive layer in the same plating tank in which the second conductive layer is formed.

13 . The method of claim 12 , wherein the forming of the first conductive layer and the second conductive layer comprises differently applying a plating condition in which the first conductive layer is formed and a plating condition in which the second conductive layer is formed to simultaneously form the first conductive layer and the second conductive layer having different thicknesses.

14 . The method of claim 12 , wherein each of the first and second conductive layers is formed of a metal including gold.

15 . The method of claim 12 , wherein the forming of the first pad and the second pad comprises:
forming a first pattern, formed of a metal including copper, on the first and second plating seed layers, respectively, preprocessing an upper surface of the formed first pattern to have a curvature, and forming a second pattern, formed of a metal including copper, having a thickness thinner than the first pattern on the preprocessed first pattern.

16 . The method of claim 15 , wherein the first conductive layer includes a first region in contact with the first pad and a second region spaced apart from the first pad,
wherein the first region of the first conductive layer and the second region of the first conductive layer are monolithically formed with each other, wherein the second region of the first conductive layer comprises a portion of the first conductive layer that is bent in an inward direction. wherein the second conductive layer includes a third region in contact with the second pad and a fourth region spaced apart from the second pad, wherein the third region of the second conductive layer and the fourth region of the second conductive layer are monolithically formed with each other, wherein the fourth region of the second conductive layer comprises a portion of the second conductive layer that is bent in an inward direction.

17 . The method of claim 16 , wherein the first conductive layer is connected to a wire, and wherein the second conductive layer is conne

Assignees

• Lg Innotek Co Ltd

Inventors

• Cho Sung Oh
• Kim Yoon Tai

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W90/701 Primary

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W70/685

  comprising multiple insulating layers · CPC title

• H10W70/66

  Conductive materials thereof · CPC title