Pixel circuit and display panel

US2021090489A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2021090489-A1
Application numberUS-202016880203-A
CountryUS
Kind codeA1
Filing dateMay 21, 2020
Priority dateSep 25, 2019
Publication dateMar 25, 2021
Grant date

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A pixel circuit including a writing circuit, a compensation circuit, a reset circuit, a brightness control circuit, and a light emission control circuit is provided. The writing circuit provides a first data signal and a second data signal. A first compensation unit of the compensation circuit provides, in a first time period, a first driving current according to the first data signal. A second compensation unit of the compensation circuit provides, in a second time period separated from the first time period, a second driving current according to the second data signal. The reset circuit provides a reference voltage to the compensation circuit. The light emission control circuit conducts the first compensation unit to the brightness control circuit in the first time period, and conducts the second compensation unit to the brightness control circuit in the second time period.

First claim

Opening claim text (preview).

What is claimed is: 1 . A pixel circuit, comprising: a writing circuit, configured to provide a first data signal and a second data signal; a compensation circuit, comprising a first compensation unit and a second compensation unit, wherein the first compensation unit is configured to provide, in a first time period, a first driving current according to the first data signal, the second compensation unit is configured to provide, in a second time period, a second driving current according to the second data signal, and the first time period is separated from the second time period; a reset circuit, configured to provide a reference voltage to the compensation circuit; a brightness control circuit; and a light emission control circuit, coupled with the first compensation unit, the second compensation unit, and the brightness control circuit, wherein the light emission control circuit conducts, in the first time period, the first compensation unit to the brightness control circuit so that the brightness control circuit emits light according to the first driving current, and the light emission control circuit conducts, in the second time period, the second compensation unit to the brightness control circuit so that the brightness control circuit emits light according to the second driving current. 2 . The pixel circuit of claim 1 , wherein the light emission control circuit comprises: a first emission switch, comprising a first terminal, a second terminal, and a control terminal, wherein the first terminal of the first emission switch is coupled with the first compensation unit, and the control terminal of the first emission switch is configured to receive a first emission signal; and a second emission switch, comprising a first terminal, a second terminal, and a control terminal, wherein the first terminal of the second emission switch is coupled with the second compensation unit, and the control terminal of the second emission switch is configured to receive a second emission signal, wherein the second terminal of the first emission switch and the second terminal of the second emission switch are coupled, in a parallel connection, with the brightness control circuit. 3 . The pixel circuit of claim 1 , wherein the reset circuit comprises: a first reset switch, comprising a first terminal, a second terminal, and a control terminal, wherein the first terminal of the first reset switch is coupled with the first compensation unit, and the control terminal of the first reset switch is configured to receive a first reset signal; and a second reset switch, comprising a first terminal, a second terminal, and a control terminal, wherein the first terminal of the second reset switch is coupled with the second compensation unit, and the control terminal of the second reset switch is configured to receive a second reset signal, wherein the second terminal of the first reset switch and the second terminal of the second reset switch are configured to receive the reference voltage. 4 . The pixel circuit of claim 1 , wherein the writing circuit comprises: a first node, configured to provide the first data signal; a first writing switch, comprising a first terminal, a second terminal, and a control terminal; a second writing switch, comprising a first terminal, a second terminal, and a control terminal, wherein the first terminal of the first writing switch and the first terminal of the second writing switch are coupled with the first node; a second node, configured to provide the second data signal; a third writing switch, comprising a first terminal, a second terminal, and a control terminal; and a fourth writing switch, comprising a first terminal, a second terminal, and a control terminal, wherein the first terminal of the third writing switch and the first terminal of the fourth writing switch are coupled with the second node, wherein the second terminal of the first writing switch and the second terminal of the third writing switch are coupled with a data line, and the second terminal of the second writing switch and the second terminal of the fourth writing switch are configured to receive the reference voltage, the control terminal of the first writing switch and the control terminal of the fourth writing switch are configured to receive a first emission signal, and the control terminal of the second writing switch and the control terminal of the third writing switch are configured to receive a second emission signal. 5 . The pixel circuit of claim 4 , wherein the first emission signal is opposite to the second emission signal. 6 . The pixel circuit of claim 4 , wherein the writing circuit is configured to receive a plurality of data voltages from the data line, when the writing circuit outputs the reference voltage as the first data signal, the writing circuit outputs the plurality of data voltages as the second data signal and the second compensation unit determines magnitude of the second driving current according to a corresponding one of the plurality of data voltages. 7 . The pixel circuit of claim 1 , wherein the first compensation unit comprises: a first driving transistor, comprising a first terminal, a second terminal, and a control terminal; a first compensation switch, comprising a first terminal, a second terminal, and a control terminal, wherein the first terminal of the first compensation switch is coupled with the control terminal of the first driving transistor, the second terminal of the first compensation switch is coupled with the second terminal of the first driving transistor, and the control terminal of the first compensation switch is configured to receive a first scan signal; and a first capacitor, coupled between the writing circuit and the control terminal of the first driving transistor, and configured to receive the first data signal, wherein the second compensation unit comprises: a second driving transistor, comprising a first terminal, a second terminal, and a control terminal; a second compensation switch, comprising a first terminal, a second terminal, and a control terminal, wherein the first terminal of the second compensation switch is coupled with the control terminal of the second driving transistor, the second terminal of the second compensation switch is coupled with the second terminal of the second driving transistor, and the control terminal of the second compensation switch is configured to receive a second scan signal; and a second capacitor, coupled between the writing circuit and the control terminal of the second driving transistor, and configured to receive the second data signal, wherein the first terminal of the first driving transistor and the first terminal of the second driving transistor are coupled, in a parallel connection, with a first power terminal. 8 . The pixel circuit of claim 1 , wherein the brightness control circuit comprises: an input terminal, coupled with the light emission control circuit, and configured to receive the first driving current or the second driving current; a first light emission element; and a second light emission element, wherein a first terminal of the first light emission element and a first terminal of the second light emission element are coupled, in a parallel connection, with the input terminal. 9 . The pixel circuit of claim 8 , wherein the brightness control circuit further comprises a resistor element, the resistor element is coupled between a second terminal of the second light emission element and a second power terminal, and a second terminal of the first light emission element is coupled with the second power terminal. 10 . The pixel circuit of claim 8 , wherein the brightn

Assignees

Inventors

Classifications

  • used for counteracting undesired variations, e.g. feedback or autozeroing · CPC title

  • by time modulation using two or more time intervals · CPC title

  • with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes · CPC title

  • Improved aperture ratio, e.g. by size reduction of the pixel circuit, e.g. for improving the pixel density or the maximum displayable luminance or brightness · CPC title

  • Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes · CPC title

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What does patent US2021090489A1 cover?
A pixel circuit including a writing circuit, a compensation circuit, a reset circuit, a brightness control circuit, and a light emission control circuit is provided. The writing circuit provides a first data signal and a second data signal. A first compensation unit of the compensation circuit provides, in a first time period, a first driving current according to the first data signal. A second…
Who is the assignee on this patent?
Au Optronics Corp
What technology area does this patent fall under?
Primary CPC classification G09G3/32. Mapped technology areas include Physics.
When was this patent published?
Publication date Thu Mar 25 2021 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).