Memory device and method of reading data

Patent metadata

Field	Value
Publication number	US-2021074364-A1
Application number	US-202017099678-A
Country	US
Kind code	A1
Filing date	Nov 16, 2020
Priority date	Sep 20, 2018
Publication date	Mar 11, 2021
Grant date	—

Abstract

A non-volatile memory includes a memory cell region including an outer region proximate a first end of the memory cell region and an inner region separated from the first end by the outer region, first and second bit lines, an outer memory cell string including memory cells connected to an outer pillar extending vertically upward through the outer region, and an inner memory cell string including memory cells connected to an inner pillar extending vertically upward through the inner region, and a data input/output (I/O). The data I/O circuit includes a page buffer circuit that connects the first bit line during a first read operation directed to memory cells of the outer memory cell string, and connects the second bit line during a second read operation directed to memory cells of the inner memory cell string, and a read voltage determination unit that selects a first optimal read voltage used during the first read operation, and a second optimal read voltage used during the second read operation.

First claim

What is claimed is:

1 . A non-volatile memory, comprising:
a memory cell region extending in a first horizontal direction and including an outer region proximate a first end of the memory cell region and an inner region separated from the first end by the outer region, wherein an arrangement of the first end, the outer region and the inner region extends in a second horizontal direction that is orthogonal to the first horizontal direction; an inner memory cell string including memory cells connected to an inner pillar extending vertically upward through the inner region; an outer memory cell string including memory cells connected to an outer pillar extending vertically upward through the outer region; a first bit line connected to the inner pillar and extending in the second horizontal direction; a second bit line connected to the outer pillar and extending in the second horizontal direction; and a page buffer circuit including a first latch and a second latch. wherein the first latch is connected to the first bit line and configured to sense first data in the inner memory cell string using a first sensing developing time, and the second latch is connected to the second bit line and configured to sense second data in the outer memory cell string using a second sensing developing time different from the first sensing developing time.

2 . The non-volatile memory of claim 1 , wherein
the page buffer circuit includes a first page buffer circuit connected to the first bit line, the first page buffer circuit includes the first latch and a third latch, the third latch is connected to the first bit line and configured to sense third data in the inner memory cell string using a third sensing developing time different from the first developing time.

3 . The non-volatile memory of claim 2 , wherein
the page buffer circuit further includes a second page buffer circuit connected to the second bit line, the second page buffer circuit includes the second latch and a fourth latch, the fourth latch is connected to the second bit line and configured to sense fourth data in the outer memory cell string using a fourth sensing developing time different from the second developing time.

4 . The non-volatile memory of claim 3 , further comprising:
a data input/output (I/O) circuit including the page buffer circuit, wherein the data I/O circuit performs a first mass bit counting for the first data in the first latch and the third data in the third latch, and a second mass bit counting for the second data in the second latch and the fourth data in the fourth latch.

5 . The non-volatile memory of claim 4 , wherein
the data I/O circuit outputs a first output data based on the first mass bit counting and a second output data based on the second mass bit counting.

6 . The non-volatile memory of claim 3 , wherein
the first page buffer circuit includes a plurality of first page buffers and the second page buffer circuit includes a plurality of second page buffers.

7 . The non-volatile memory of claim 1 , wherein
the page buffer circuit includes a first page buffer circuit connected to the first bit line, the first page buffer circuit includes the first latch and a plurality of first candidate latches, the plurality of first candidate latches are connected to the first bit line and configured to sense a plurality of candidate first data in the inner memory cell string using a plurality of first candidate sensing developing time different from the first developing time.

8 . The non-volatile memory of claim 7 , further comprising:
a data input/output (I/O) circuit including the page buffer circuit, wherein the data I/O circuit selects a first optimal read voltage to be used during a first read operation for the inner memory cell string using the first data in the first latch and the plurality of candidate first data in the plurality of first candidate latches.

9 . The non-volatile memory of claim 8 , wherein
the page buffer circuit further includes a second page buffer circuit connected to the second bit line, the second page buffer circuit includes the second latch and a plurality of second candidate latches, the plurality of second candidate latches are connected to the second bit line and configured to sense a plurality of candidate second data in the outer memory cell string using a plurality of second candidate sensing developing time different from the second developing time.

10 . The non-volatile memory of claim 9 wherein the data I/O circuit selects a second optimal read voltage to be used during a second read operation for the outer memory cell string using the second data in the second latch and the plurality of candidate second data in the plurality of second candidate latches.

11 . A non-volatile memory, comprising:
a memory cell region extending in a first horizontal direction and including an outer region proximate a first end of the memory cell region and an inner region separated from the first end by the outer region, wherein an arrangement of the first end, the outer region and the inner region extends in a second horizontal direction that is orthogonal to the first horizontal direction; an inner memory cell string including memory cells connected to an inner pillar extending vertically upward through the inner region; an outer memory cell string including memory cells connected to an outer pillar extending vertically upward through the outer region; a first bit line connected to the inner pillar and extending in the second horizontal direction; a second bit line connected to the outer pillar and extending in the second horizontal direction; and a data input/output (I/O) circuit comprising
a first page buffer circuit connected to the first bit line,
a second page buffer circuit connected to the second bit line,
wherein the first page buffer circuit includes a first latch configured to sense first data in the inner memory cell string using a first sensing developing time, and a second latch configured to sense second data in the inner memory cell string using a second sensing developing time different from the first sensing developing time, and the second page buffer circuit includes a third latch configured to sense third data in the outer memory cell string using a third sensing developing time, and a fourth latch configured to sense fourth data in the outer memory cell string using a fourth sensing developing time different from the third sensing developing time.

12 . The non-volatile memory of claim 11 , wherein
the data I/O circuit selects a first optimal read voltage to be used during a first read operation for the inner memory cell string using the first data in the first latch and the second data in the second latch. the data I/O circuit selects a second optimal read voltage to be used during a second read operation for the outer memory cell string using the third data in the third latch and the fourth data in the fourth latch.

13 . The non-volatile memory of claim 12 , wherein the first optimal read voltage is different from the second optimal read voltage.

14 . The non-volatile memory of claim 11 , wherein
the data I/O circuit performs a first mass bit counting for the first data in the first latch and the second data in the second latch, and a second mass bit counting for the third data in the third latch and the fourth data in the fourth latch.

15 . The non-volatile memory of claim 14 , wherein
the data I/O circuit outputs a first output data based on the first mass bit counting and a second output data based on the second mass bit

Assignees

• Samsung Electronics Co Ltd

Inventors

• Jeon Su Chang
• Kim Seung Bum
• Lee Ji Young

Classifications

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/10 Primary

  Programming or data input circuits · CPC title

• G11C8/14

  Word line organisation; Word line lay-out · CPC title

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title