Programmable slave circuit on a communication bus

Patent metadata

Field	Value
Publication number	US-2021064557-A1
Application number	US-202017009064-A
Country	US
Kind code	A1
Filing date	Sep 1, 2020
Priority date	Sep 3, 2019
Publication date	Mar 4, 2021
Grant date	—

Abstract

A programmable slave circuit on a communication bus is provided. In a non-limiting example, the communication bus can be a radio frequency front-end (RFFE) bus operating based on a master-slave topology and the programmable slave circuit can be an RFFE slave circuit on the RFFE bus. The programmable slave circuit is configured to receive a high-level command(s) (e.g., a macro word) over the communication bus. A processing circuit in the programmable slave circuit is programmed to generate a low-level command(s) (e.g., a bitmap word) for controlling a coupled circuit(s) based on the high-level command(s). In this regard, it is possible to program or reprogram the processing circuit, for example via over-the-air (OTA) updates, based on the high-level command(s) to be supported, thus making it possible to flexibly customize the programmable slave circuit according to operating requirements and configurations.

First claim

What is claimed is:

1 . A programmable slave circuit comprising:
a data memory circuit configured to store one or more high-level commands and one or more low-level commands; a bus interface circuit coupled to a communication bus and configured to:
receive the one or more high-level commands via the communication bus; and
write the one or more high-level commands into the data memory circuit; and
a processing circuit configured to:
read the one or more high-level commands from the data memory circuit;
generate the one or more low-level commands based on the one or more high-level commands; and
write the one or more low-level commands into the data memory circuit.

2 . The programmable slave circuit of claim 1 further comprising a program memory circuit coupled to the processing circuit and configured to store one or more pre-programmed sequences each corresponding to a respective one of the one or more high-level commands.

3 . The programmable slave circuit of claim 2 wherein each of the one or more pre-programmed sequences comprises a microcode operation corresponding to at least one operation code (opcode) selected from the group consisting of: LOAD, STORE, ADD, SUBTRACT, OR, AND, EXOR, SHIFT, JUMP, and MOVE.

4 . The programmable slave circuit of claim 2 configured to operate in a programming mode, wherein the bus interface circuit is further configured to:
receive the one or more pre-programmed sequences via the communication bus; and
cause the one or more pre-programmed sequences to be written into the program memory circuit.

5 . The programmable slave circuit of claim 2 wherein the processing circuit is further configured to:
read the one or more high-level commands from the data memory circuit; and
execute a respective one of the one or more pre-programmed sequences corresponding to each of the one or more high-level commands to generate the one or more low-level commands.

6 . The programmable slave circuit of claim 5 wherein the processing circuit comprises:
a command queue coupled to the data memory circuit and configured to store the respective one of the one or more pre-programmed sequences corresponding to each of the one or more high-level commands; and
a microcode processor configured to execute the respective one of the one or more pre-programmed sequences corresponding to each of the one or more high-level commands to generate the one or more low-level commands.

7 . The programmable slave circuit of claim 6 wherein the microcode processor comprises an arithmetic logic unit (ALU).

8 . The programmable slave circuit of claim 5 wherein the processing circuit is further configured to:
read the one or more high-level commands from the data memory circuit in response to receiving one or more interrupt service routings (ISRs) from the data memory circuit; and
execute a respective one of the one or more pre-programmed sequences corresponding to each of the one or more high-level commands to generate the one or more low-level commands.

9 . The programmable slave circuit of claim 8 wherein the processing circuit is further configured to prioritize the one or more ISRs.

10 . The programmable slave circuit of claim 8 wherein the data memory circuit comprises a memory controller configured to generate the ISR in response to any of the one or more high-level commands being written into the data memory circuit.

11 . The programmable slave circuit of claim 10 wherein the data memory circuit further comprises:
a high-level command region configured to store the one or more high-level commands; and
a low-level command region configured to store the one or more low-level commands.

12 . The programmable slave circuit of claim 11 wherein the high-level command region and the low-level command region each comprises a respective set of registers.

13 . The programmable slave circuit of claim 11 wherein the bus interface circuit is further configured to read the one or more high-level commands and the one or more low-level commands.

14 . The programmable slave circuit of claim 11 wherein the bus interface circuit and the processing circuit are each configured to write to both the high-level command region and the low-level command region.

15 . The programmable slave circuit of claim 11 wherein:
the bus interface circuit is configured to write exclusively to the high-level command region; and
the processing circuit is configured to write exclusively to the low-level command region.

16 . The programmable slave circuit of claim 1 further comprising a write control circuit configured to:
receive the one or more high-level commands from the bus interface circuit;
receive the one or more low-level commands from the processing circuit; and
write the one or more high-level commands and the one or more low-level commands into the data memory circuit sequentially.

17 . The programmable slave circuit of claim 16 wherein the write control circuit comprises:
a first-in first-out (FIFO) queue configured to store the one or more high-level commands and the one or more low-level commands; and
a command serializer configured to:
read one of the one or more high-level commands and the one or more low-level commands from the FIFO queue; and
write the one of the one or more high-level commands and the one or more low-level commands into the data memory circuit.

18 . The programmable slave circuit of claim 1 further comprising a front-end circuit coupled to the data memory circuit and configured to control one or more coupled circuits based on the one or more low-level commands.

19 . The programmable slave circuit of claim 1 wherein:
the communication bus comprises a radio frequency front-end (RFFE) bus; and
the bus interface circuit is coupled to an RFFE master via the RFFE bus.

20 . The programmable slave circuit of claim 19 wherein:
the one or more high-level commands each comprises a macro word configured according to a predefined macro format; and
the one or more low-level commands each comprises an RFFE bitmap word conforming to a predefined RFFE format.

Assignees

• Qorvo Us Inc

Inventors

• Ngo Christopher Truong
• Khlat Nadim
• Hietala Alexander Wayne

Classifications

• H04L12/40019

  Details regarding a bus master · CPC title

• G06F13/364 Primary

  using independent requests or grants, e.g. using separated request and grant lines · CPC title

• G06F13/4282

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

• G06F9/30032

  Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE · CPC title

• G06F9/30043

  LOAD or STORE instructions; Clear instruction · CPC title