Single chip signal isolator

Patent metadata

Field	Value
Publication number	US-2021057330-A1
Application number	US-201916547823-A
Country	US
Kind code	A1
Filing date	Aug 22, 2019
Priority date	Aug 22, 2019
Publication date	Feb 25, 2021
Grant date	—

Abstract

Methods and apparatus for a signal isolator IC package including a die having a first die portion isolated from a second die portion. The first die portion is surrounded on six sides by first insulative material and the second die portion is surrounded on six sides by second insulative material. The first die portion provides a first voltage domain and the second die portion provides a second voltage domain. The signal isolator comprises a first signal path between the first die portion and the second die portion, wherein the first signal path is isolated with respect to the first and second die portions.

First claim

What is claimed is:

1 . A signal isolator IC package, comprising:
a die having a first die portion and a second die portion, wherein the first and second die portions are electrically isolated, wherein the first die portion is surrounded on six sides by first insulative material and the second die portion is surrounded on six sides by second insulative material, wherein the first die portion provides a first voltage domain and the second die portion provides a second voltage domain, wherein the signal isolator comprises a first signal path between the first die portion and the second die portion, wherein the first signal path is isolated with respect to the first and second die portions.

2 . The signal isolator IC package according to claim 1 , wherein the die comprises a single die processed to provide the first and second die portions.

3 . The signal isolator IC package according to claim 1 , wherein the first signal path is bi-directional.

4 . The signal isolator IC package according to claim 1 , wherein the first and second die portions are separated by a trench filled with insulative material.

5 . The signal isolator IC package according to claim 1 , wherein the first path includes first and second capacitors having a common plate.

6 . The signal isolator IC package according to claim 5 , wherein the first capacitor comprises first and second plates separated by a first dielectric layer, and the second capacitor comprises a third plate and the second plate.

7 . The signal isolator IC package according to claim 6 , wherein the second plate overlaps the first plate and the third plate.

8 . The signal isolator IC package according to claim 7 , wherein the first dielectric layer separates the first plate and the second plate.

9 . The signal isolator IC package according to claim 1 , wherein the first and second die portions are separated on respective four lateral sides by a trench filled with insulating material.

10 . The signal isolator IC package according to claim 1 , wherein the first signal path includes coils to provide isolated inductive coupling of the first and second die portions.

11 . The signal isolator IC package according to claim 1 , wherein active circuit devices are not placed within a keep-out area, where the first path includes first and second capacitors having a common plate, and wherein the first capacitor comprises first and second plates separated by a first dielectric layer, and the second capacitor comprises a third plate and the second plate, wherein the keep-out area is defined by the second plate.

12 . The signal isolator IC package according to claim 1 , wherein the first signal path is configured for On-Off keying (OOK) modulation.

13 . The signal isolator IC package according to claim 1 , wherein the first die portion includes a safe-state module to detect a lack of carrier signal.

14 . The signal isolator IC package according to claim 13 , wherein the safe-state module transitions one or more output pins of the IC package to a high impedance state upon detection of an error condition.

15 . A method, comprising:
employing a die for a signal isolator IC package, the die having a first die portion and a second die portion, wherein the first and second die portions are electrically isolated, wherein the first die portion is surrounded on six sides by first insulative material and the second die portion is surrounded on six sides by second insulative material, wherein the first die portion provides a first voltage domain and the second die portion provides a second voltage domain, and wherein the signal isolator comprises a first signal path between the first die portion and the second die portion, wherein the first signal path is isolated with respect to the first and second die portions.

16 . The method according to claim 15 , wherein the die comprises a single die processed to provide the first and second die portions.

17 . The method according to claim 15 , wherein the first signal path is bi-directional.

18 . The method according to claim 15 , wherein the first and second die portions are separated by a trench filled with insulative material.

19 . The method according to claim 15 , wherein the first path includes first and second capacitors having a common plate.

20 . The method according to claim 19 , wherein the first capacitor comprises first and second plates separated by a first dielectric layer, and the second capacitor comprises a third plate and the second plate.

21 . The method according to claim 20 , wherein the second plate overlaps the first plate and the third plate.

22 . The method according to claim 21 , wherein the first dielectric layer separates the first plate and the second plate.

23 . The method according to claim 15 , wherein the first and second die portions are separated on respective four lateral sides by a trench filled with insulating material.

24 . The method according to claim 15 , wherein the first signal path includes coils to provide isolated inductive coupling of the first and second die portions.

25 . The method according to claim 15 , wherein active circuit devices are not placed within a keep-out area, where the first path includes first and second capacitors having a common plate, and wherein the first capacitor comprises first and second plates separated by a first dielectric layer, and the second capacitor comprises a third plate and the second plate, wherein the keep-out area is defined by the second plate.

26 . The method according to claim 15 , wherein the first signal path is configured for On-Off keying (OOK) modulation.

27 . The method according to claim 15 , wherein the first die portion includes a safe-state module to detect a lack of carrier signal.

28 . The method according to claim 27 , wherein the safe-state module transitions one or more output pins of the IC package to a high impedance state upon detection of an error condition.

29 . A signal isolator IC package, comprising:
a die means for providing circuitry, the die means having a first die portion and a second die portion, wherein the first and second die portions are electrically isolated, wherein the first die portion is surrounded on six sides by first insulative material and the second die portion is surrounded on six sides by second insulative material, wherein the first die portion provides a first voltage domain and the second die portion provides a second voltage domain, wherein the signal isolator comprises a first signal path between the first die portion and the second die portion, wherein the first signal path is isolated with respect to the first and second die portions.

30 . The signal isolator IC package according to claim 29 , wherein the first path includes first and second capacitors having a common plate.

31 . The signal isolator IC package according to claim 30 , wherein the first capacitor comprises first and second plates separated by a first dielectric layer, and the second capacitor comprises a third plate and the second plate.

32 . The signal isolator IC package according to claim 31 , wherein the second plate overlaps the first plate and the third plate.

33 . The signal isolator IC package according to claim 32 , wherein the first d

Assignees

• Allegro Microsystems Llc

Inventors

• Briano Robert A
• Uberti Bruno Luis
• Milesi Alejandro Gabriel
• Monreal Gerardo A

Classifications

• H10W44/20

  at high-frequency [HF] or radio frequency [RF] · CPC title

• H10W20/497

  Inductive arrangements or effects of, or between, wiring layers · CPC title

• H10W20/496 Primary

  Capacitor integral with wiring layers · CPC title

• H10W44/601

  Capacitive arrangements (H10W44/20 takes precedence) · CPC title

• H10W20/495

  Capacitive arrangements or effects of, or between wiring layers · CPC title