Reducing processor resource consumption for memory access and enabling shared memory access

Patent metadata

Field	Value
Publication number	US-2021056055-A1
Application number	US-201916550004-A
Country	US
Kind code	A1
Filing date	Aug 23, 2019
Priority date	Aug 23, 2019
Publication date	Feb 25, 2021
Grant date	—

Abstract

An apparatus for memory management a high-speed fabric controller and a memory controller connected between a high-speed memory and a processor. The memory controller is configured to control processor access to the high-speed memory over a memory bus between the processor and the high-speed memory. The apparatus includes a high-speed data connection between the memory controller and the high-speed fabric controller and a data connection between a tier of persistent data storage and the high-speed fabric controller. The high-speed fabric controller is configured to control data transfers between the tier of persistent data storage over and the high-speed memory independent of the processor.

First claim

What is claimed is:

1 . An apparatus comprising:
a high-speed fabric controller; a memory controller connected between a high-speed memory and a processor, the memory controller configured to control processor access to the high-speed memory over a memory bus between the processor and the high-speed memory; a high-speed data connection between the memory controller and the high-speed fabric controller; and a data connection between a tier of persistent data storage and the high-speed fabric controller, wherein the high-speed fabric controller configured to control data transfers between the tier of persistent data storage over and the high-speed memory independent of the processor.

2 . The apparatus of claim 1 , wherein the high-speed fabric controller is configured to transfer data between the high-speed memory and the tier of persistent data storage without the data passing through the processor.

3 . The apparatus of claim 1 , further comprising a data connection between the processor and the high-speed fabric controller.

4 . The apparatus of claim 1 , wherein the high-speed fabric controller is configured to control data transfers between the tier of persistent data storage over and the high-speed memory over the high-speed data connection.

5 . The apparatus of claim 1 , wherein the high-speed data connection is a first high-speed data connection, the processor is a first processor, the memory controller is a first memory controller and the high-speed memory is a first high-speed memory and further comprising a second high-speed data connection between the high-speed fabric controller and a second memory controller connected between to a second high-speed memory and a second processor, the second memory controller configured to control second processor access to the second high-speed memory over a memory bus between the second processor and the second high-speed memory and wherein the high-speed fabric controller is configured to control data transfers between one or more of the first high-speed memory, the tier of persistent data storage and the second high-speed memory independent of the first processor and the second processor.

6 . The apparatus of claim 5 , wherein the high-speed fabric controller is configured to manage spare data capacity of the first high-speed memory and the second high-speed memory to share spare data capacity so that spare data capacity of the first high-speed memory and the second high-speed memory is less than spare data capacities of not sharing spare data capacity.

7 . The apparatus of claim 1 , wherein the tier of persistent data storage is a first tier of persistent data storage and further comprising one or more additional tiers of persistent data storage and wherein the high-speed fabric controller further comprises a data tiering aggregator that is configured to control data tiering between the high-speed memory, the first tier of persistent data storage and the one or more additional tiers of persistent data storage.

8 . The apparatus of claim 7 , wherein the data tiering aggregator is configured to manage data tiering independent of caching instructions from the processor.

9 . The apparatus of claim 7 , wherein the processor comprises a pre-fetch queue and requests data caching through the pre-fetch queue and the data tiering aggregator accesses the pre-fetch queue to fulfil caching requests from the processor.

10 . The apparatus of claim 7 , wherein the first tier of persistent data storage and the one or more additional tiers of persistent data storage are connected to the high-speed fabric controller over a high-speed data connection.

11 . The apparatus of claim 7 , wherein the high-speed memory and each tier of persistent data storage comprise a different data storage speed and the data tiering aggregator is configured to manage data tiering based on data storage speeds of the high-speed memory and each tier of persistent data storage.

12 . The apparatus of claim 7 , wherein the data tiering aggregator is configured to present data to the processor as a single data source without respect to a data tier of data storage controlled by the high-speed fabric controller.

13 . The apparatus of claim 1 , wherein data connection between the memory controller and the processor comprises a parallel memory interface.

14 . The apparatus of claim 1 , wherein the memory controller is configured to respond to commands from the processor and the high-speed fabric controller.

15 . An apparatus comprising:
a high-speed fabric controller comprising a data tiering aggregator; a memory controller connected between a high-speed memory and a processor, the memory controller configured to control processor access to the high-speed memory over a memory bus between the processor and the high-speed memory; a high-speed data connection between the memory controller and the high-speed fabric controller; a data connection between a first tier of persistent data storage and the high-speed fabric controller; and a data connection between each of one or more additional tiers of persistent data storage and the high-speed fabric controller; a data connection between the processor and the high-speed fabric controller, wherein the data tiering aggregator is configured to control data tiering between the high-speed memory, the first tier of persistent data storage and the one or more additional tiers of persistent data storage, and wherein the high-speed fabric controller is configured to control data transfers between the tier of persistent data storage over and the high-speed memory independent of the processor without the data passing through the processor.

16 . The apparatus of claim 15 , wherein the data tiering aggregator is configured to manage data tiering independent of caching instructions from the processor.

17 . The apparatus of claim 15 , wherein the high-speed memory and each tier of persistent data storage comprise a different data storage speed and the data tiering aggregator is configured to manage data tiering based on the data storage speeds of the high-speed memory and each tier of persistent data storage.

18 . The apparatus of claim 15 , wherein the data tiering aggregator is configured to present data to the processor as a single data source without respect to a data tier of data storage controlled by the high-speed fabric controller.

19 . A system comprising:
a processor; a high-speed memory connected to the processor over a memory bus; a high-speed fabric controller; a memory controller connected between the high-speed memory and the processor, the memory controller configured to control processor access to the high-speed memory over the memory bus; a high-speed data connection between the memory controller and the high-speed fabric controller; and a data connection between each of one or more tiers of persistent data storage and the high-speed fabric controller, wherein the high-speed fabric controller is configured to control data transfers between the one or more tiers of persistent data storage over and the high-speed memory independent of the processor.

20 . The system of claim 19 , wherein the high-speed data connection is a first high-speed data connection, the processor is a first processor, the memory controller is a first memory controller and the high-speed memory is a first high-speed memory, the system further comprising a second processor, a second high-speed memory, a second high-speed data connection between the high-s

Assignees

• Lenovo Entpr Solutions Singapore Pte Ltd

Inventors

• Hamilton Jeffrey R
• Bahali Sumanta K
• Seidel Peter R
• Bigelow Brian E
• Hernandez Juan Q

Classifications

• G06F3/0685

  Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays · CPC title

• G06F3/0649

  Lifecycle management · CPC title

• G06F3/061

  Improving I/O performance · CPC title

• G06F13/1673 Primary

  using buffers · CPC title

• G06F13/36

  for access to common bus or bus system · CPC title