Magnetic memory device

Patent metadata

Field	Value
Publication number	US-2021050508-A1
Application number	US-202016829216-A
Country	US
Kind code	A1
Filing date	Mar 25, 2020
Priority date	Aug 14, 2019
Publication date	Feb 18, 2021
Grant date	—

Abstract

A magnetic memory device includes a device isolation layer on a substrate and defining an active region, a source region and a drain region apart from each other in the active region of the substrate, a channel portion in the active region of the substrate and between the source region and the drain region, a spin orbit torque (SOT)-inducing layer on the channel portion of the substrate, a magnetic tunnel junction (MTJ) structure on the SOT-inducing layer, the MTJ structure including a free layer on the SOT-inducing layer, a tunnel barrier layer on the free layer, and a pinned layer on the tunnel barrier, a word line on the MTJ structure, a source line electrically connected to the source region, and a bit line electrically connected to the drain region.

First claim

What is claimed is:

1 . A magnetic memory device, comprising:
a device isolation layer on a substrate and defining an active region; a source region and a drain region apart from each other in the active region of the substrate; a channel portion in the active region of the substrate and between the source region and the drain region; a spin orbit torque (SOT)-inducing layer on the channel portion of the substrate; a magnetic tunnel junction (MTJ) structure on the SOT-inducing layer, the MTJ structure including:
a free layer on the SOT-inducing layer,
a tunnel barrier layer on the free layer, and
a pinned layer on the tunnel barrier layer;
a word line on the MTJ structure; a source line electrically connected to the source region; and a bit line electrically connected to the drain region.

2 . The magnetic memory device as claimed in claim 1 , wherein an entire upper surface of the MTJ structure is covered by the word line.

3 . The magnetic memory device as claimed in claim 1 , wherein the SOT-inducing layer includes one or more of tungsten, platinum, tantalum, hafnium, rhenium, iridium, gold, silver, titanium, copper, bismuth telluride, bismuth selenide, antimony telluride, molybdenum sulfide, molybdenum telluride, tungsten sulfide, or tungsten telluride.

4 . The magnetic memory device as claimed in claim 1 , wherein the magnetic memory device is configured such that, in a write operation, a write current flows from the source region to the drain region through the channel portion and the SOT-inducing layer.

5 . The magnetic memory device as claimed in claim 4 , wherein the magnetic memory device is configured such that, in the write operation, a spin current is transmitted by a spin-orbit coupling characteristic to the free layer in contact with the SOT-inducing layer when the write current flows through the SOT-inducing layer.

6 . The magnetic memory device as claimed in claim 1 , wherein the magnetic memory device is configured such that, in a read operation, a read current flows from the word line to the drain region through the MTJ structure and the SOT-inducing layer.

7 . The magnetic memory device as claimed in claim 1 , wherein an upper surface of the word line is disposed at a level higher than an upper surface of the MTJ structure and an upper surface of the SOT-inducing layer based on an upper surface of the substrate.

8 . The magnetic memory device as claimed in claim 1 , wherein an entire bottom surface of the SOT-inducing layer is in contact with an upper surface of the channel portion.

9 . The magnetic memory device as claimed in claim 1 , further comprising a metal silicide layer between the SOT-inducing layer and an upper surface of the substrate.

10 . The magnetic memory device as claimed in claim 1 , further comprising an insulating spacer between the SOT-inducing layer and the MTJ structure.

11 . The magnetic memory device as claimed in claim 10 , wherein:
the insulating spacer includes a magnetic insulator, and the magnetic insulator includes one or more of yttrium iron garnet, nickel ferrite, manganese ferric oxide, nickel zinc ferrite, or manganese zinc ferrite.

12 . A magnetic memory device, comprising:
a device isolation layer on a substrate and defining a plurality of active regions; a source region and a drain region apart from each other in each of the plurality of active regions; a channel portion between the source region and the drain region; a plurality of magnetic memory units respectively formed on the channel portion; and a word line on the plurality of magnetic memory units and extending in a first direction parallel to an upper surface of the substrate, wherein: each of the plurality of magnetic memory units includes:
a spin orbit torque (SOT)-inducing layer on the channel portion; and
a magnetic tunnel junction (MTJ) structure on the SOT-inducing layer, the MTJ structure including a free layer, a tunnel barrier layer, and a pinned layer, and
the word line is disposed at a level higher than that of the MTJ structure.

13 . The magnetic memory device as claimed in claim 12 , wherein:
the plurality of magnetic memory units include a first magnetic memory unit and a second magnetic memory unit that are apart from each other in the first direction, the word line covers both an upper surface of the first magnetic memory unit and an upper surface of the second magnetic memory unit, and a first SOT-inducing layer included in the first magnetic memory unit is apart from a second SOT-inducing layer included in the second magnetic memory unit.

14 . The magnetic memory device as claimed in claim 13 , further comprising an insulating layer surrounding sidewalls of the first magnetic memory unit and the second magnetic memory unit,
wherein sidewalls of the first SOT-inducing layer and the second SOT-inducing layer are surrounded by the insulating layer.

15 . The magnetic memory device as claimed in claim 12 , wherein:
the plurality of magnetic memory units include a first magnetic memory unit and a second magnetic memory unit that are apart from each other in the first direction, the word line covers both an upper surface of the first magnetic memory unit and an upper surface of the second magnetic memory unit, and the SOT-inducing layer included in the first magnetic memory unit is connected to the SOT-inducing layer included in the second magnetic memory unit.

16 . The magnetic memory device as claimed in claim 15 , wherein the SOT-inducing layer vertically overlaps the plurality of active regions and extends in the first direction.

17 . A magnetic memory device, comprising:
a channel portion on a substrate and including a compound semiconductor; a source region and a drain region on the substrate and apart from each other with the channel portion therebetween; an insulating spacer on the channel portion and including a magnetic insulator; a magnetic tunnel junction (MTJ) structure on the insulating spacer, the MTJ structure including:
a free layer on the insulating spacer,
a tunnel barrier layer on the free layer, and
a pinned layer on the tunnel barrier layer;
a word line on the MTJ structure; a source line electrically connected to the source region; and a bit line electrically connected to the drain region.

18 . The magnetic memory device as claimed in claim 17 , wherein the channel portion includes the compound semiconductor in which a spin orbit torque (SOT)-inducing dopant is included at a first concentration, the compound semiconductor including at least one of a Group III-V semiconductor and a Group II-VI semiconductor.

19 . The magnetic memory device as claimed in claim 18 , wherein the SOT-inducing dopant includes one or more of gallium, aluminum, indium, boron, or phosphorus.

20 . The magnetic memory device as claimed in claim 17 , wherein:
the magnetic memory device is configured such that, in a write operation, a write current flows from the source region to the drain region through the channel portion in a write operation, and is configured such that, in the write operation, a spin current is transmitted to the free layer by a spin-orbit coupling characteristic via the insulating spacer in contact with the channel portion when the write current flows through the channel portion.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Seowon
• Moon Junghwan
• Bak Junghoon
• Kim Woojin
• Hong Hyeongsun

Classifications

• H10N50/85

  Materials of the active region · CPC title

• H01F10/329

  Spin-exchange coupled multilayers wherein the magnetisation of the free layer is switched by a spin-polarised current, e.g. spin torque effect · CPC title

• H01F10/3254

  the spacer being semiconducting or insulating, e.g. for spin tunnel junction [STJ] · CPC title

• G11C11/1657

  Word-line or row circuits · CPC title

• G11C11/1675

  Writing or programming circuits or methods · CPC title