Thin film transistor, pixel structure, display device and manufacturing method

Patent metadata

Field	Value
Publication number	US-2021028315-A1
Application number	US-201916641078-A
Country	US
Kind code	A1
Filing date	Feb 22, 2019
Priority date	Feb 22, 2019
Publication date	Jan 28, 2021
Grant date	—

Abstract

The present disclosure provides a thin film transistor, a pixel structure, a display device, and a manufacturing method. The thin film transistor includes: a gate on the substrate; a gate insulating layer covering the gate and the substrate; a first support portion and a second support portion, which are provided on the gate insulating layer covering the substrate and located on both sides of the gate, wherein the first support portion is not connected to the second support portion; a semiconductor layer on the first support portion, the second support portion, and the gate insulating layer covering the gate; and a source and a drain respectively connected to the semiconductor layer. The first support portion and the second support portion are respectively configured to support the semiconductor layer.

First claim

1 . A thin film transistor provided on a substrate, comprising:
a gate on the substrate; a gate insulating layer covering the gate and the substrate; a first support portion and a second support portion, which are provided on the gate insulating layer covering the substrate and located on both sides of the gate, wherein the first support portion is not connected to the second support portion; a semiconductor layer on the first support portion, the second support portion, and the gate insulating layer covering the gate; and a source and a drain each connected to the semiconductor layer; wherein the first support portion and the second support portion each are configured to support the semiconductor layer.

2 . The thin film transistor according to claim 1 , wherein:
surfaces on a side of the first support portion and the second support portion facing away from the substrate are flush with a surface on a side of a portion of the gate insulating layer on the gate facing away from the substrate; and the first support portion and the second support portion are provided at a step formed by the gate insulating layer on both sides of the gate, and extending directions of the first support portion and the second support portion are the same as that of the semiconductor layer.

3 . The thin film transistor according to claim 2 , wherein
an orthographic projection of the semiconductor layer on the substrate is located inside an orthographic projection of the gate, the first support portion, and the second support portion on the substrate.

4 . The thin film transistor according to claim 1 , wherein
the source is above the first support portion, and the drain is above the second support portion.

5 . The thin film transistor according to claim 1 , wherein
materials of the first support portion and the second support portion comprise a conductive material, the first support portion serves as the source, and the second support portion serves as the drain.

6 . The thin film transistor according to claim 5 , wherein
the conductive material comprises a metal material; and a solid solution of a metal and a semiconductor material is formed in areas where the first support portion and the second support portion are in contact with the semiconductor layer respectively.

7 . The thin film transistor according to claim 6 , wherein
the metal material comprises aluminum; a material of the semiconductor layer comprises polysilicon; and the solid solution is a solid solution of silicon and aluminum.

8 . The thin film transistor according to claim 1 , wherein
a material of the gate insulating layer comprises MgO.

9 . A pixel structure, comprising:
the thin film transistor according to claim 1 .

10 . An array substrate, comprising the thin film transistor according to claim 1 .

11 . A display device, comprising the array substrate according to claim 10 .

12 . A manufacturing method for a thin film transistor, comprising:
forming a gate on a substrate; forming a gate insulating layer covering the gate and the substrate; forming a first support portion and a second support portion on the gate insulating layer covering the substrate and located on both sides of the gate, wherein the first support portion is not connected to the second support portion; forming a semiconductor layer on the first support portion, the second support portion, and the gate insulating layer covering the gate; and forming a source and a drain each connected to the semiconductor layer; wherein the first support portion and the second support portion each are configured to support the semiconductor layer.

13 . The manufacturing method according to claim 12 , further comprising:
performing an annealing treatment on the semiconductor layer.

14 . The manufacturing method according to claim 13 , wherein after performing the annealing treatment, the manufacturing method further comprises:
doping an area of the semiconductor layer on the first support portion and an area of the semiconductor layer on the second support portion; and forming the source and the drain respectively connected to the semiconductor layer in respective doped areas, wherein the source and the drain respectively form an ohmic contact with the respective doped areas.

15 . The manufacturing method according to claim 13 , wherein
materials of the first support portion and the second support portion comprise a conductive material, the first support portion serves as the source, and the second support portion serves as the drain.

16 . The manufacturing method according to claim 15 , wherein
the conductive material comprises a metal material; before performing the annealing treatment on the semiconductor layer, a material of the semiconductor layer comprises amorphous silicon; and the performing the annealing treatment on the semiconductor layer comprises: annealing the semiconductor layer by a laser annealing process to convert the amorphous silicon into polysilicon, wherein, by the laser annealing process, a solid solution of a metal and a semiconductor material is also formed in areas where the first support portion and the second support portion are in contact with the semiconductor layer respectively so as to form an ohmic contact.

17 . The manufacturing method according to claim 16 , wherein
the metal material comprises aluminum; and the solid solution is a solid solution of silicon and aluminum.

Assignees

• Boe Technology Group Co Ltd

Inventors

• Qiang Zhaohui
• Guan Feng
• Wang Zhi
• Gao Yupeng
• Lyu Yang
• Li Chao
• Du Jianhua
• Chen Lei

Classifications

• H10D30/0321

  comprising silicon, e.g. amorphous silicon or polysilicon · CPC title

• H10D30/6739

  Conductor-insulator-semiconductor electrodes · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D30/6743

  Silicon · CPC title

• H10D30/6737

  characterised by the electrode materials · CPC title