Semiconductor devices and methods of fabricating the same

Patent metadata

Field	Value
Publication number	US-2021020631-A1
Application number	US-202017030556-A
Country	US
Kind code	A1
Filing date	Sep 24, 2020
Priority date	Oct 30, 2015
Publication date	Jan 21, 2021
Grant date	—

Abstract

Semiconductor device having less defects in a gate insulating film and improved reliability and methods of forming the semiconductor devices are provided. The semiconductor devices may include a gate insulating film on a substrate and a gate electrode structure on the gate insulating film. The gate electrode structure may include a lower conductive film, a silicon oxide film, and an upper conductive film sequentially stacked on the gate insulating film. The lower conductive film may include a barrier metal layer.

First claim

What is claimed is:

1 . A method of fabricating a semiconductor device, the method comprising:
forming a gate insulating layer on a substrate; sequentially forming a lower gate electrode and a silicon layer on the gate insulating layer; oxidizing the silicon layer to form a silicon oxide layer; performing a heat treatment process while the silicon oxide layer is exposed; and forming an upper gate electrode on the silicon oxide layer after performing the heat treatment process.

2 . The method of claim 1 , wherein forming the lower gate electrode comprises forming a barrier metal layer.

3 . The method of claim 2 , wherein forming the barrier metal layer and forming the silicon layer are performed without exposing the substrate to oxygen.

4 . The method of claim 2 , wherein the silicon layer is formed to directly contact the barrier metal layer.

5 . The method of claim 1 , wherein oxidizing the silicon layer comprises oxidizing an upper portion of the silicon layer, and a lower portion of the silicon layer remains between the silicon oxide layer and the lower gate electrode after oxidizing the silicon layer.

6 . The method of claim 1 , further comprising:
removing the upper gate electrode using the silicon oxide layer as an etch stopping layer.

7 . A method of fabricating a semiconductor device, the method comprising:
forming a first gate insulating layer on a first region of a substrate and forming a second gate insulating layer on a second region of the substrate; sequentially forming a first lower gate electrode and a first silicon layer on the first gate insulating layer and sequentially forming a second lower gate electrode and a second silicon layer on the second gate insulating layer; oxidizing the first silicon layer to form a first silicon oxide layer and oxidizing the second silicon layer to form a second silicon oxide layer; performing a heat treatment process while the first and second silicon oxide layers are exposed; forming a first conductive layer on the first silicon oxide layer and forming a second conductive layer on the second silicon oxide layer after performing the heat treatment process; removing the first conductive layer using the first silicon oxide layer as an etch stopping layer; and forming a third conductive layer on the first silicon oxide layer and forming a fourth conductive layer on the second conductive layer after removing the first conductive layer.

8 . The method of claim 7 , wherein sequentially forming the first lower gate electrode and the first silicon layer comprises sequentially forming a first barrier metal layer and the first silicon layer without exposing the substrate to oxygen, and sequentially forming the second lower gate electrode and the second silicon layer comprises sequentially forming a second barrier metal layer and the second silicon layer without exposing the substrate to oxygen.

9 . The method of claim 8 , wherein the first silicon layer is formed to directly contact the first barrier metal layer, and
wherein the second silicon layer is formed to directly contact the second barrier metal layer.

10 . The method of claim 7 , wherein oxidizing the first silicon layer comprises oxidizing an upper portion of the first silicon layer, and a lower portion of the first silicon layer remains between the first silicon oxide layer and the first lower gate electrode after oxidizing the first silicon layer, and
wherein oxidizing the second silicon layer comprises oxidizing an upper portion of the second silicon layer, and a lower portion of the second silicon layer remains between the second silicon oxide layer and the second lower gate electrode after oxidizing the second silicon layer.

11 . A method of forming an integrated circuit device, the method comprising:
sequentially forming a gate insulating layer and a barrier metal layer on a substrate; forming a silicon oxide layer on the barrier metal layer; and forming a gate electrode on the silicon oxide layer, the silicon oxide layer being between the barrier metal layer and the gate electrode.

12 . The method of claim 11 , wherein forming the silicon oxide layer comprises:
forming a silicon layer on the barrier metal layer; and oxidizing the silicon layer.

13 . The method of claim 12 , wherein forming the barrier metal layer and forming the silicon layer are performed without exposing the substrate to oxygen.

14 . The method of claim 12 , wherein the silicon layer directly contacts the barrier metal layer.

15 . The method of claim 14 , wherein the barrier metal layer comprises a titanium nitride (TiN) layer.

16 . The method of claim 12 , wherein oxidizing the silicon layer comprises oxidizing an upper portion of the silicon layer, and a lower portion of the silicon layer remains between the silicon oxide layer and the barrier metal layer after oxidizing the silicon layer.

17 . The method of claim 11 , further comprising:
performing a heat treatment process after forming the silicon oxide layer while the silicon oxide layer is exposed.

18 . The method of claim 17 , wherein the gate insulating layer comprises a high-k material.

19 . The method of claim 11 , further comprising removing the gate electrode using the silicon oxide layer as an etch stopping layer.

20 . The method of claim 11 , further comprising forming an insulation layer on the substrate before forming the gate insulating layer and the barrier metal layer,
wherein the insulation layer comprises a recess exposing the substrate, and wherein the barrier metal layer and the silicon oxide layer are conformally formed along an inner surface of the recess.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Park Moon-Kyu
• Song Jae-Yeol
• Na Hoon-Joo
• Hwang Yoon-Tae
• Yoon Ki-joong
• Hyun Sang-Jin

Classifications

• H10P14/6544

  to change the morphology of the insulating materials, e.g. transformation of an amorphous layer into a crystalline layer · CPC title

• H10P14/6536

  by exposure to radiation, e.g. visible light · CPC title

• H10D84/853

  comprising FinFETs · CPC title

• H10D84/0193

  the components including FinFETs · CPC title

• H10D84/0167

  Manufacturing their channels · CPC title