System for cancelling interference in a full-duplex wireline communication link

Patent metadata

Field	Value
Publication number	US-2021006277-A1
Application number	US-202016914628-A
Country	US
Kind code	A1
Filing date	Jun 29, 2020
Priority date	Jun 28, 2019
Publication date	Jan 7, 2021
Grant date	—

Abstract

The present invention relates to a system for cancelling interference in a full-duplex wireline communication link. The communication link has a transceiver at each end and configured to transmit a signal and receive a signal. The transceiver comprises: a self-interference (SI) canceller module configured to subtract self-interference of the signal transmitted by the transceiver from the signal received by the same transceiver in analog domain; and an echo canceller module configured to subtract reflected version of the signal transmitted by the transceiver from the signal received by the same transceiver in analog domain.

First claim

What is claimed is:

1 . A system for cancelling interference in a full-duplex wireline communication link having a transceiver at each end of the communication link configured to transmit a signal and receive a signal, the transceiver comprising:
a self-interference (SI) canceller module configured to subtract self-interference of the signal transmitted by the transceiver from the signal received by the same transceiver in analog domain; and an echo canceller module configured to subtract reflected version of the signal transmitted by the transceiver from the signal received by the same transceiver in analog domain.

2 . The system as claimed in claim 1 , wherein the SI canceller module comprises:
a plurality of delay elements, each delay element configured to receive the signal transmitted by the transceiver and generate a delayed replica of the transmitted signal; a plurality of multipliers with adjustable weight coefficients, each of the multiplier configured to receive and amplify the delayed replica of the transmitted signal; and a summation circuit configured to subtract output of the multipliers from the signal received by the transceiver in analog domain.

3 . The system as claimed in claim 1 , wherein the echo canceller module comprises:
a plurality of delay elements, each delay element configured to receive the signal transmitted by the transceiver and generate a delayed replica of the transmitted signal; a plurality of multipliers with adjustable weight coefficients, each of the multiplier configured to receive and amplify the delayed replica of the transmitted signal; and a summation circuit configured to subtract output of the multipliers from the signal received by the transceiver in analog domain.

4 . The system as claimed in claim 1 , wherein the SI canceller module and the echo canceller module for a given transceiver are configured to adapt its weight coefficients in the background without imposing any restriction on the signal transmitted by a far-end transceiver.

5 . The system as claimed in claim 2 , comprising a correlator configured to determine a correlation between the output of the SI canceller module and each delayed replica of the transmitted signal, the correlator having a plurality of multipliers and a plurality of integrators configured to adaptively adjust weight coefficients of each of the multipliers of the SI canceller module.

6 . The system as claimed in claim 5 , wherein the correlator has an adjustable rate at which gains of the multipliers are updated.

7 . The system as claimed in claim 3 , comprising a correlator configured to determine a correlation between the output of the echo canceller module and each delayed replica of the transmitted signal, the correlator having a plurality of multipliers and a plurality of integrators configured to adaptively adjust weight coefficients of each of the multipliers of the echo canceller module.

8 . The system as claimed in claim 7 , wherein the correlator has an adjustable rate at which gains of the multipliers are updated.

9 . The system as claimed in claim 1 , comprising a residual SI and echo cancellation module configured to cancel residual SI and echo, in digital domain of the transceiver, caused due to any long-delayed reflection of the transmitted signal in the channel.

10 . The system as claimed in claim 9 , wherein the residual SI and echo cancellation module is configured to cancel residual SI and echo, in the digital domain, remaining after cancellation performed by the SI canceller module and echo canceller module in the analog domain of the transceiver.

11 . The system as claimed in claim 10 , wherein the residual SI and echo cancellation module comprising:
a plurality of delay elements, each delay element configured to receive the signal transmitted by the transceiver and generate a delayed replica of the transmitted signal; a plurality of multipliers with adjustable weight coefficients, each of the multiplier configured to receive and amplify the delayed replica of the transmitted signal; and a summation circuit configured to subtract output of the multipliers from the signal received by the transceiver in the digital domain.

12 . The system as claimed in claim 11 , wherein the residual SI and echo cancellation module comprises a correlator configured to determine a correlation between the output of the residual SI and echo cancellation module and each delayed replica of the transmitted signal, the correlator having a plurality of multipliers and a plurality of integrators configured to adaptively adjust weight coefficients of each of the multipliers of the residual SI and echo cancellation module.

13 . The system as claimed in claim 12 , wherein the correlator has an adjustable rate at which gains of the multipliers are updated.

14 . The system as claimed in claim 1 , wherein the SI canceller module, the echo canceller module, the residual SI and echo cancellation module are fabricated on a single integrated chip.

15 . A full-duplex wireline communication channel comprising:
two transceivers, one at each end of the communication link, configured to simultaneously transmit and receive data; each of the transceivers coupled with: an SI canceller module as claimed in preceding claims and configured to subtract self-interference of a signal transmitted by a transceiver from a signal received by the same transceiver in analog domain; and an echo canceller module configured as claimed in preceding claims and configured to subtract reflected version of the signal transmitted by the transceiver from the signal received by the same transceiver in analog domain.

16 . The full-duplex wireless communication channel as claimed in claim 15 , wherein each of the two transceivers transmits over the same frequency band.

17 . The full-duplex wireless communication channel as claimed in claim 15 , wherein bandwidth of each of the signals transmitted through the channel is more than one octave.

18 . The full-duplex wireless communication channel as claimed in claim 15 , wherein baud-rates used by transmitters of the two transceivers are independent of each other.

19 . The full-duplex wireless communication channel as claimed in claim 15 , wherein modulation formats used by transmitters of the two transceivers are M1-PAM and M2-PAM, wherein values of M1 and M2 are independent of each other, each being an integer of value 2 or more.

Assignees

• Indian Inst Technology Bombay

Inventors

• Gupta Shalabh
• Agarwal Pranav
• Goyal Sandeep

Classifications

• H04B1/525

  with means for reducing leakage of transmitter signal into the receiver · CPC title

• H04B1/123 Primary

  using adaptive balancing or compensation means (adaptive filter circuits and algorithms H03H) · CPC title

• H04L5/14

  Two-way operation using the same type of signal, i.e. duplex · CPC title