Semiconductor memory device, controller, memory system, and operation method thereof

Patent metadata

Field	Value
Publication number	US-2021004289-A1
Application number	US-202017029912-A
Country	US
Kind code	A1
Filing date	Sep 23, 2020
Priority date	Oct 24, 2018
Publication date	Jan 7, 2021
Grant date	—

Abstract

Disclosed are a semiconductor memory device, a controller, a memory system, and an operation method thereof. The semiconductor memory device includes a memory cell array including a plurality of memory cells, and an error correcting code (ECC) decoder configured to receive first data and a parity output from selected memory cells of the memory cell array. The ECC decoder generates a syndrome based on the first data and the parity, generates a decoding status flag (DSF) indicating a type of an error of the first data by the syndrome, and outputs the second data and the DSF to an external device outside of the semiconductor memory device when a read operation of the semiconductor memory device is performed.

First claim

What is claimed is:

1 . An operation method of a semiconductor memory device comprising:
during a read operation of the semiconductor memory device, receiving first data and a parity output from selected memory cells of a memory cell array; generating a syndrome based on the first data and the parity; generating second data and a decoding status flag (DSF) indicating a type of an error of the first data by the syndrome; and outputting the second data and the DSF to an external device outside of the semiconductor memory device, wherein a number of bits of the first data is the same as a number of bits of the second data.

2 . The operation method of the semiconductor memory device of claim 1 , further comprising:
during a write operation of the semiconductor memory device, receiving third data from the external device; generating the parity; and outputting fourth data and the parity to the selected memory cells, wherein a number of bits of the third data is the same as a number of bits of the fourth data.

3 . The operation method of the semiconductor memory device of claim 2 , wherein the generating of the parity comprises:
performing an exclusive OR (XOR) operation on each of row vectors of a first H matrix and on the third data and then perform a modulo 2 operation thereon to generate the parity, and wherein codes of column vectors of the first H matrix have different codes including “0” and “1,” that are not all “0,” and a minimum Hamming distance between the codes of the first H matrix is three.

4 . The operation method of the semiconductor memory device of claim 1 , wherein the generating of the second data and the DSF comprises:
outputting the first data as the second data when the syndrome indicates a non-error; correcting a corresponding bit of the first data and the parity and then outputting the corrected data as the second data when the syndrome indicates a correctable error; and generating the DSF having a first state when the syndrome indicates the non-error or the correctable error and a second state when the syndrome indicates an uncorrectable error.

5 . The operation method of the semiconductor memory device of claim 4 , wherein the second data and the DSF are output to the outside of the semiconductor memory device in series or in parallel when the read operation is performed.

6 . The operation method of the semiconductor memory device of claim 1 , wherein the generating of the syndrome based on the first data and the parity comprises:
performing an XOR operation on each of row vectors of a second H matrix, and the first data and the parity and then performing a modulo 2 operation thereon to generate a predetermined number of bits of syndrome, and wherein the generating of the second data and the DSF comprises: detecting a non-error, a correctable error, or an uncorrectable error using the syndrome; detecting a position of column vector of the second H matrix in which the syndrome is present to generate error position information when the correctable error is detected; correcting errors of the first data and the parity on the basis of the error position information when the correctable error is detected; and generating the DSF of a first state when the non-error or the correctable error is detected and generate the DSF of a second state when the uncorrectable error is detected.

7 . The operation method of the semiconductor memory device of claim 6 , wherein codes of column vectors of the second H matrix have different codes including “0” and “1,” that are not all “0,” and a minimum Hamming distance between the codes of the second H matrix is three.

8 . An operation method of a controller comprising:
performing an ECC decoding operation selected from among a plurality of ECC decoding operations on first data applied from an external device outside of the controller in response to a decoding status flag (DSF) applied from the external device and indicating a type of an error of the first data; and generating second data and an error signal by performing the selected ECC decoding operation, wherein the first data and the DSF are provided from an outside of the controller, and wherein a number of bits of the first data is the same as a number of bits of the second data.

9 . The operation method of the controller of claim 8 , wherein the performing of the ECC decoding operation comprises:
performing a first ECC decoding operation in response to the DSF of a first state; and performing a second ECC decoding operation in response to the DSF of a second state, wherein the first ECC decoding operation is an error detection operation, and wherein the second ECC decoding operation is an error correction and detection operation.

10 . The operation method of the controller of claim 9 , wherein the performing of the first ECC decoding operation comprises:
receiving the first data; generating a first predetermined number of bits of first syndrome; and detecting that the first syndrome indicates a non-error or a 3-bit or less error, wherein the performing of the second ECC decoding operation comprises: receiving the first data; generating the first predetermined number of bits of second syndrome; and detecting that the second syndrome indicates a non-error or a 2-bit or less error, wherein, when the second syndrome indicates the non-error, the performing of the second ECC decoding operation comprises transmitting data excluding a parity with a predetermined number of bits included in the first data, and wherein, when the second syndrome indicates the 2-bit or less error, the performing of the second ECC decoding operation comprises detecting an error position of the first data to generate error position information using the second syndrome, correcting an error of the first data using the error position information, and then transmitting corrected data excluding the parity.

11 . The operation method of the controller of claim 10 , wherein the performing of the first ECC decoding operation comprises:
performing an exclusive OR (XOR) operation on each of row vectors of a first H matrix and the first data and then perform a modulo 2 operation thereon to generate the first syndrome; and detecting the non-error or the 3-bit or less error using the first syndrome.

12 . The operation method of the controller of claim 11 , wherein the performing of the second ECC decoding operation comprises:
performing an XOR operation on each of row vectors of a second H matrix and the first data and then performing a modulo 2 operation thereon to generate the first predetermined number of bits of second syndrome; detecting the non-error or the 2-bit or less error using the second syndrome; detecting a position of column vector of the second H matrix in which the second syndrome is present to generate error position information when the 2-bit or less error is detected; and correcting an error of the first data on the basis of the error position information when the 2-bit or less error is detected.

13 . The operation method of the controller of claim 12 , wherein codes of column vectors of the first H matrix and the second H matrix have different codes including “0” and “1,” that are not all “0,” and a minimum Hamming distance between the codes of the first H matrix and a minimum Hamming distance between the codes of the second H matrix are four.

14 . The operation method of the controller of claim 8 , wherein the performing of the ECC decoding operation comprises:
performing an exclusive OR (XOR) operation on each of row vectors of an H matrix and the first data and

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Myung Kyu
• Kong Jun Jin
• Lee Ki Jun
• Cho Sung Hye
• Kim Dae Hyun
• Chu Yong Gyu

Classifications

• G11C2029/0411

  Online error correction · CPC title

• G11C29/52

  Protection of memory contents; Detection of errors in memory contents · CPC title

• G06F11/1048

  using arrangements adapted for a specific error detection or correction feature · CPC title

• G06F11/1068 Primary

  in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence) · CPC title

• G11C29/42 Primary

  using error correcting codes [ECC] or parity check · CPC title