Bit slicer circuit for s-fsk receiver, integrated circuit, and method associated therewith

Patent metadata

Field	Value
Publication number	US-2020412588-A1
Application number	US-202017018366-A
Country	US
Kind code	A1
Filing date	Sep 11, 2020
Priority date	Feb 12, 2019
Publication date	Dec 31, 2020
Grant date	—

Abstract

An integrated circuit includes a bit slicing circuit with a processing circuit. The processing circuit receives discrete frequency power estimates based on an S-FSK waveform received by an S-FSK receiver associated with the bit slicing circuit. The discrete frequency power estimates are representative of digital logic levels in a series of data frames modulated using S-FSK to form the S-FSK waveform. Each data frame including at least one word. Each word includes bit periods. The processing circuit receives SNR parameters that represent a dynamic SNR for the respective discrete frequency power estimates in relation to the series of data frames. The processing circuit selects a bit slicing technique from a set of available bit slicing techniques to generate data bit values for bit periods of the discrete frequency power estimates based on the SNR parameters. A method for performing bit slicing in an S-FSK receiver is also disclosed.

First claim

1 . A processing circuit comprising:
a mark frequency power estimate input; a space frequency power estimate input, the space frequency being different than the mark frequency; a trinary data output; mark binary amplitude shift key circuitry coupled to the inputs and having an output coupled to the trinary output; space binary amplitude shift key circuitry coupled to the inputs and having an output coupled to the trinary output; and parallel binary amplitude shift key circuitry coupled to the inputs and having an output coupled to the trinary output.

2 . The processing circuit of claim 1 in which the mark frequency power estimate input, and the space frequency power estimate input are adapted to receive “ON” and “OFF” logic level signals.

3 . The processing circuit of claim 1 in which the trinary output provides Barker code values.

4 . The processing circuit of claim 1 including a mark frequency signal to noise ratio input, and a mark frequency threshold input coupled to the mark binary amplitude shift key circuitry and the space binary amplitude shift key circuitry.

5 . The processing circuit of claim 1 including a space frequency signal to noise ratio input, and a space frequency threshold input coupled to the mark binary amplitude shift key circuitry mark binary amplitude shift key circuitry.

6 . The processing circuit of claim 1 including a mark frequency signal to noise ratio input, a mark frequency threshold input, a space frequency signal to noise ratio input, and a space frequency threshold input coupled to the mark binary amplitude shift key circuitry and the space binary amplitude shift key circuitry.

7 . The processing circuit of claim 1 in which the trinary output carries one of a +1 value, a 0 (zero) value, and a −1 value.

8 . The processing circuit of claim 1 including zero energy circuitry coupled to the inputs and having an output coupled to the trinary data output, the zero energy circuitry providing a Barker code value of 0 to the trinary output.

9 . The processing circuit of claim 1 in which the mark binary amplitude shift key circuitry provides a Barker code value output of +1 or −1 to the trinary output.

10 . The processing circuit of claim 1 in which the space binary amplitude shift key circuitry provides a Barker code value output of +1 or −1 to the trinary output.

11 . The processing circuit of claim 1 in which the parallel binary amplitude shift key circuitry provides a Barker code value output of +1, 0, or −1 to the trinary output.

12 . The processing circuit of claim 1 in which the mark frequency power estimate input and the space frequency power estimate input are coupled to a power line.

13 . The processing circuit of claim 1 in which the mark frequency power estimate input and the space frequency power estimate input are coupled to a power line of a photovoltaic array.

14 . The processing circuit of claim 1 including correlator circuitry having an input coupled to the trinary output and having an intermediate control output.

15 . The processing circuit of claim 14 including keep alive circuitry having an input coupled to the intermediate control output.

16 . A process of operating an integrated circuit comprising:
receiving mark frequency power estimate signals, that include noise, for individual data bit periods and simultaneously receiving space frequency power estimate signals, that include noise, for the individual data bit periods, the space frequency being different than the mark frequency; providing, for the data bit periods, mark signal to noise ratio signals and space signal to noise ratio signals; producing Barker code value outputs of +1 or −1 using mark binary amplitude shift key circuitry in response to the receiving and the providing; producing Barker code value outputs of +1 or −1 using space binary amplitude shift key circuitry in response to the receiving and the providing; and producing Barker code value outputs of +1, 0, or −1 using parallel binary amplitude shift key circuitry in response to the receiving and the providing.

17 . The process of claim 16 including producing Barker code value outputs of 0 in response to the receiving and the providing using zero energy circuitry.

18 . The process of claim 16 in which the providing mark signal to noise ratio signals includes providing the mark signal to noise ratio signals from the mark frequency power estimate signals.

19 . The process of claim 16 in which the providing mark signal to noise ratio signals includes providing the mark signal to noise ratio signals by subtracting the off-power from the on-power of the mark frequency power estimate signals.

20 . The process of claim 16 in which the providing space signal to noise ratio signals includes providing the space signal to noise ratio signals from the space frequency power estimate signals.

21 . The process of claim 16 in which the providing space signal to noise ratio signals includes providing the space signal to noise ratio signals by subtracting the off-power from the on-power of the space frequency power estimate signals.

22 . The process of claim 16 including providing mark threshold signals from the mark frequency power estimate signals by dividing by 2 the difference between the off-power and the on-power of the mark frequency power estimate signals.

23 . The process of claim 16 including providing space threshold signals from the space frequency power estimate signals.

24 . The process of claim 16 including providing space threshold signals from the space frequency power estimate signals by dividing by 2 the difference between the off-power and the on-power of the space frequency power estimate signals.

25 . The process of claim 16 in which:
the providing mark signal to noise ratio signals includes providing the mark signal to noise ratio signals from the mark frequency power estimate signals;
the providing space signal to noise ratio signals includes providing the space signal to noise ratio signals from the space frequency power estimate signals; and including:
providing mark threshold signals from the mark frequency power estimate signals;
providing space threshold signals from the space frequency power estimate signals; and
providing the Barker codes in response to the frequency power estimates, the signal to noise ratios, and the threshold signals.

26 . The processing circuit of claim 16 including correlator circuitry correlating the Barker code values into intermediate control signals.

27 . The processing circuit of claim 26 including keep alive circuitry generating communication signals from the intermediate control signals.

Assignees

• Texas Instruments Inc

Inventors

• Klemmer Nikolaus
• Akour Amneh Mohammed
• Patki Abhijit Anant
• Pauletti Timothy Patrick
• Pande Tarkesh

Classifications

• H04L27/14 Primary

  Demodulator circuits; Receiver circuits · CPC title

• H04B1/69

  Spread spectrum techniques · CPC title

• H04L27/12

  Modulator circuits; Transmitter circuits · CPC title

• H04L27/06

  Demodulator circuits; Receiver circuits · CPC title

• H04B1/16 Primary

  Circuits · CPC title