Array substrate, manufacturing method thereof, and display device

Patent metadata

Field	Value
Publication number	US-2020411619-A1
Application number	US-202016905899-A
Country	US
Kind code	A1
Filing date	Jun 18, 2020
Priority date	Jun 28, 2019
Publication date	Dec 31, 2020
Grant date	—

Abstract

An array substrate, a manufacturing method thereof, and a display device are provided. The array substrate includes: a base substrate; a first signal line on the base substrate; a first buffer layer provided on the base substrate and covering the first signal line; a second signal line on a side of the first buffer layer facing away from the base substrate; a first insulating layer provided on the base substrate and covering the second signal line; and a thin film transistor on a side of the first insulating layer facing away from the base substrate, the thin film transistor including a gate electrode, a source electrode and a drain electrode. A thickness of the first signal line is greater than that of the gate electrode, and a thickness of the second signal line is greater than that of the source electrode or the drain electrode.

First claim

What is claimed is:

1 . An array substrate, comprising:
a base substrate; a first signal line on the base substrate; a first buffer layer provided on the base substrate and covering the first signal line; a second signal line on a side of the first buffer layer facing away from the base substrate; a first insulating layer provided on the base substrate and covering the second signal line; and a thin film transistor on a side of the first insulating layer facing away from the base substrate, the thin film transistor comprising a gate electrode, a source electrode and a drain electrode, wherein a thickness of the first signal line is greater than a thickness of the gate electrode of the thin film transistor, and a thickness of the second signal line is greater than a thickness of the source electrode or the drain electrode of the thin film transistor.

2 . The array substrate of claim 1 , wherein the thickness of the first signal line is at least 1.5 times of the thickness of the gate electrode of the thin film transistor, and the thickness of the second signal line is at least 1.5 times of the thickness of the source electrode or the drain electrode of the thin film transistor.

3 . The array substrate of claim 1 , wherein the first signal line and the second signal line each comprise a copper-based metal.

4 . The array substrate of claim 1 , wherein the first signal line comprises a gate line, and the second signal line comprises a power supply line or a data line.

5 . The array substrate of claim 1 , wherein the first insulating layer comprises a first interlayer dielectric layer and a second buffer layer, the first interlayer dielectric layer is disposed on both sides of the second signal line, and the second buffer layer is disposed on a side of the first interlayer dielectric layer facing away from the base substrate and covers the second signal line; and
an orthographic projection of the thin film transistor on the base substrate does not overlap with an orthographic projection of the first interlayer dielectric layer on the base substrate.

6 . The array substrate of claim 5 , further comprising a light shielding layer between the first buffer layer and the second buffer layer,
wherein the orthographic projection of the thin film transistor on the base substrate at least partially overlaps with an orthographic projection of the light shielding layer on the base substrate, and the orthographic projection of the light shielding layer on the base substrate does not overlap with the orthographic projection of the first interlayer dielectric layer on the base substrate.

7 . The array substrate of claim 6 , wherein the first buffer layer comprises a recessed area, the recessed area is recessed toward the base substrate, and an orthographic projection of each of the thin film transistor and the light shielding layer on the first buffer layer falls within the recessed area.

8 . The array substrate of claim 6 , wherein the array substrate further comprises:
a second interlayer dielectric layer, the second interlayer dielectric layer being disposed on a side of the second buffer layer facing away from the base substrate; a first conductive plug which is disposed in a via hole penetrating the first buffer layer, located on a side of the first signal line away from the base substrate, and electrically connected to the first signal line; and a second conductive plug in a first via hole penetrating both the second buffer layer and the second interlayer dielectric layer, the second conductive plug electrically being connected to the first signal line through the first conductive plug.

9 . The array substrate of claim 8 , wherein the thin film transistor comprises a switching transistor, and the first signal line is electrically connected to a gate electrode of the switching transistor through both the first conductive plug and the second conductive plug.

10 . The array substrate of claim 9 , wherein the array substrate further comprises:
a third conductive plug in a second via hole penetrating through both the second buffer layer and the second interlayer dielectric layer, one of the source electrode and the drain electrode being electrically connected to the second signal line through the third conductive plug.

11 . The array substrate of claim 10 , wherein the thin film transistor further comprises a driving transistor; and
the second signal line comprises a data line and a power supply line, the data line is electrically connected to one of a source electrode and a drain electrode of the switching transistor, and the power supply line is electrically connected to one of a source electrode and a drain electrode of the driving transistor.

12 . The array substrate of claim 11 , wherein the other one of the source electrode and the drain electrode of the switching transistor is electrically connected to a gate electrode of the driving transistor.

13 . The array substrate of claim 8 , wherein the array substrate further comprises:
a fourth conductive plug in a second via hole penetrating both the second buffer layer and the second interlayer dielectric layer, the light shielding layer being electrically connected to the second signal line through the fourth conductive plug.

14 . The array substrate of claim 13 , wherein the first conductive plug is located in the same layer as the light shielding layer, and each of the second conductive plug, the third conductive plug, and the fourth conductive plug is located in the same layer as the source electrode or the drain electrode.

15 . The array substrate of claim 10 , further comprising:
a second insulating layer on a side of the second interlayer dielectric layer facing away from the base substrate; a color film layer on a side of the second insulating layer facing away from the base substrate; a third insulating layer provided on the side of the second insulating layer facing away from the base substrate and covering the color film layer; and a first electrode on a side of the third insulating layer facing away from the base substrate, the first electrode being electrically connected to the other one of the source electrode and the drain electrode through a conductive plug in both the second insulating layer and the third insulating layer.

16 . The array substrate of claim 1 , wherein the thin film transistor is a top-gate thin film transistor.

17 . A display device comprising the array substrate of claim 1 .

18 . A method of manufacturing an array substrate, comprising:
forming a first signal line on a base substrate; forming a first buffer layer covering the first signal line on the base substrate; forming a second signal line on a side of the first buffer layer facing away from the base substrate; forming a first insulating layer covering the second signal line on the base substrate; and forming a thin film transistor on a side of the first insulating layer facing away from the base substrate, the thin film transistor comprising a gate electrode, a source electrode and a drain electrode, wherein a thickness of the first signal line is greater than a thickness of the gate electrode of the thin film transistor, and a thickness of the second signal line is greater than a thickness of the source electrode or the drain electrode of the thin film transistor.

19 . The method of claim 18 , further comprising:
forming an opening in the first interlayer dielectric layer; and through one patterning process, forming a light shielding layer on

Assignees

• Hefei Xinsheng Optoelectronics Technology Co Ltd
• Boe Technology Group Co Ltd

Inventors

• Huang Yongchao
• Cheng Jun
• Wang Dongfang
• Liu Jun
• Cheng Leilei
• Yan Liangchen

Classifications

• H10K59/124

  Insulating layers formed between TFT elements and OLED elements · CPC title

• H10K59/126 Primary

  Shielding, e.g. light-blocking means over the TFTs · CPC title

• H10D86/441

  Interconnections, e.g. scanning lines · CPC title

• H10D86/021

  of multiple TFTs · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title