Array substrate, display panel and method for driving pixel-driving circuit

Patent metadata

Field	Value
Publication number	US-2020410939-A1
Application number	US-201916710929-A
Country	US
Kind code	A1
Filing date	Dec 11, 2019
Priority date	Jun 28, 2019
Publication date	Dec 31, 2020
Grant date	—

Abstract

An array substrate includes that: a data-writing phase of each row of the pixel-driving circuits is divided into a first phase and a second phase, in the first phase, a data signal of each data line is written into a parasitic capacitor on a data wiring electrically connected to a respective one of the row of the pixel-driving circuits, and in the second phase, the corresponding scan line transmits a scan signal to the row of the pixel-driving circuits, and the parasitic capacitor on each of the data wirings electrically connected to the row of the pixel-driving circuits writes the data signal into a drive control terminal of a respective one of the pixel-driving circuits; and the first phase of each row of the pixel-driving circuits at least partially overlaps with the second phase of a previous row of the pixel-driving circuits.

First claim

What is claimed is:

1 . An array substrate, comprising:
a plurality of scan lines extending in a row direction, a plurality of data lines extending in a column direction and a plurality of pixel-driving circuits, wherein, a scan line of the plurality of scan lines corresponds to a row of the plurality of pixel-driving circuits and is electrically connected to the row of the plurality of pixel-driving circuits, a data line of the plurality of data lines corresponds to a column of the pixel-driving circuits, and wherein each of the plurality of data lines is divided into m data wirings, wherein the m data wirings are mutually independent and are sequentially arranged in a row direction, and wherein an i-th data wiring of the m data wirings is electrically connected to km+i-th rows of the plurality of pixel-driving circuits of a corresponding column of the plurality of pixel-driving circuits respectively, wherein m is a positive integer greater than or equal to 2; a data-writing phase of each row of the plurality of pixel-driving circuits is divided into a first phase and a second phase, wherein in the first phase, a data signal of each of the data lines is written into a parasitic capacitor on a respective one of the m data wirings electrically connected to a corresponding row of the plurality of pixel-driving circuits, and in the second phase, a corresponding scan line transmits a scan signal to the row of the plurality of pixel-driving circuits, and the parasitic capacitor on each of the m data wirings is electrically connected to the corresponding row of the plurality of pixel-driving circuits and writes the data signal into a drive control terminal of a respective one of the plurality of pixel-driving circuits; and the first phase of each row of the plurality pixel-driving circuits at least partially overlaps with the second phase of a previous row of the pixel-driving circuits.

2 . The array substrate of claim 1 , further comprising a multiplexer and m timing control lines, wherein the multiplexer comprises a plurality of multiplexer units;
each of the multiplexer units corresponds to a respective one of the plurality of data lines, each of the plurality of data lines comprises a data fan-out line, each of the multiplexer units comprises m switch devices, input terminals of each of the m switch devices of the each of the multiplexer units are electrically connected to the respective one of data fan-out lines, a control terminal of an i-th switch device is electrically connected to an i-th timing control line, and an output terminal of the i-th switch device is electrically connected to the i-th data wiring; and in a first phase of the km+i-th rows of the pixel-driving circuits, the i-th timing control line is configured to control the i-th switch device of each of the multiplexer units to be turned on so as to write data signal of each of the data lines into a parasitic capacitor on a corresponding i-th data wiring.

3 . The array substrate of claim 1 , wherein
a scan line electrically connected to a row of the plurality of pixel-driving circuits comprises an initialization scan line and a data-writing scan line; an effective pulse is provided for the initialization scan line in an initialization phase; and an effective pulse is provided for the data-writing scan line in at least a part of the data-writing phase, wherein the initialization phase is before the data-writing phase.

4 . The array substrate of claim 3 , wherein
m is equal to 2, the first phase of each row of the plurality of pixel-driving circuits overlaps with the second phase of a previous row of the plurality of pixel-driving circuits, and the effective pulse of the data-writing scan line is in the second phase.

5 . The array substrate of claim 4 , wherein
the initialization phase overlaps with the first phase of each row of the plurality of pixel-driving circuits.

6 . The array substrate of claim 5 , wherein an effective pulse width of the initialization scan line is equal to an effective pulse width of the data-writing scan line.

7 . The array substrate of claim 6 , further comprising:
multi-stage cascaded first shift register units, wherein one stage of the first shift register units is corresponds to one row of the plurality of pixel-driving circuits; and a trigger terminal of the one stage of the first shift register units receives a trigger signal, an output terminal of the one stage of the first shift register units is electrically connected to a corresponding scan line, the output terminal of the one stage of the first shift register units is electrically connected to a trigger terminal of a next stage of the first shift register units and is connected to an initialization scan line of a current row of the plurality of pixel-driving circuits and a data-writing scan line of a previous row of the pixel-driving circuits.

8 . The array substrate of claim 4 , wherein the effective pulse of the data-writing scan line is in the data-writing phase; and
in the first phase of the row of the pixel-driving circuits, the data signal of each of the data lines is written into the parasitic capacitor on each of the data wirings electrically connected to the row of the plurality of pixel-driving circuits, and the corresponding row of the scan lines transmits the scan signal to the row of the plurality of pixel-driving circuits to write the data signal into a drive control terminal of a drive transistor of a corresponding pixel-driving circuit through the data wirings electrically connected to the row of the plurality of pixel-driving circuits.

9 . The array substrate of claim 8 , wherein an effective pulse width of the initialization scan line is equal to an effective pulse width of the data-writing scan line.

10 . The array substrate of claim 9 , further comprising:
multi-stage cascaded first shift register units and multi-stage cascaded second shift register units, wherein, a stage of the first shift register units corresponds to an odd-numbered row of the pixel-driving circuits; and a trigger terminal of the stage of the first shift register units receives a trigger signal, an output terminal of the stage of the first shift register units is electrically connected to a corresponding scan line, the output terminal of the stage of the first shift register units is electrically connected to a trigger terminal of a next stage of the first shift register units and is connected to an initialization scan line of a current row of the plurality of pixel-driving circuits and a data-writing scan line of a previous odd-numbered row of the pixel-driving circuits; a stage of the second shift register units corresponds to an even-numbered row of the pixel-driving circuits; and a trigger terminal of the stage of the second shift register units receives a trigger signal, an output terminal of the stage of the second shift register units is electrically connected to a corresponding scan line, the output terminal of the stage of the second shift register units is electrically connected to a trigger terminal of a next stage of the second shift register units and is connected to an initialization scan line of a current row of the plurality of pixel-driving circuits and a data-writing scan line of a previous even-numbered row of the pixel-driving circuits.

11 . The array substrate of claim 8 , wherein an effective pulse width of the initialization scan line is half of an effective pulse width of the data-writing scan line.

12 . The array substrate of claim 11 , further comprising:
multi-stage cascaded first shift register units, multi-stage cascaded second shift register units and multi-stage cascad

Assignees

• Shanghai Tianma Am Oled Co Ltd

Inventors

• Li Yue
• Zhang Mengmeng

Classifications

• G09G2310/0251

  Precharge or discharge of pixel before applying new pixel voltage · CPC title

• G09G2300/0842

  forming a memory circuit, e.g. a dynamic memory with one capacitor · CPC title

• G09G3/3233

  with pixel circuitry controlling the current through the light-emitting element · CPC title

• G09G2300/0426

  Layout of electrodes and connections · CPC title

• G09G2300/0861

  with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes · CPC title