Semiconductor devices

Patent metadata

Field	Value
Publication number	US-2020402898-A1
Application number	US-202016900646-A
Country	US
Kind code	A1
Filing date	Jun 12, 2020
Priority date	Jun 20, 2019
Publication date	Dec 24, 2020
Grant date	—

Abstract

A device including a stack of layers defining a first conductor pattern at a first level of the stack and one or more semiconductor channels in respective regions, connecting a pair of parts of the first conductor pattern, and capacitively coupled via a dielectric to a coupling conductor of a second conductor pattern at a second level of the stack. The stack includes at least two insulator patterns over which the first level or second level conductor patterns is formed. A first insulator pattern occupies one or more semiconductor channel regions to provide the dielectric. The second insulator pattern defines one or more windows in the one or more semiconductor channel regions through which the second conductor pattern contacts the first insulator pattern other than via the second insulator pattern. The second insulator pattern overlaps the first insulator pattern outside the one or more semiconductor channel regions.

First claim

What is claimed is:

1 . A device, comprising: a stack of layers defining at least: a first conductor pattern at a first level of the stack; and one or more semiconductor channels in respective semiconductor channel regions, connecting a pair of parts of the first conductor pattern, and capacitively coupled via a dielectric to a coupling conductor of a second conductor pattern at a second level of the stack; wherein the stack comprises: at least two insulator patterns over which the first level conductor pattern or the second level conductor pattern is formed; wherein a first insulator pattern of the at least two insulator patterns occupies at least the one or more semiconductor channel regions to provide the dielectric; and a second insulator pattern of the at least two insulator patterns defines one or more windows in at least the one or more semiconductor channel regions through which the second conductor pattern contacts said first insulator pattern other than via the second insulator pattern; wherein the second insulator pattern overlaps the first insulator pattern outside the one or more semiconductor channel regions.

2 . The device according to claim 1 , wherein the second level conductor pattern is formed over the at least two insulator patterns; and the coupling conductor of the second level conductor pattern is formed at least over the whole area of the first insulator pattern.

3 . The device according to claim 1 , wherein the one or more windows extends over at least the whole area of the respective semiconductor channel region.

4 . The device according to claim 1 , wherein the first insulator pattern comprises a stack of insulator layers.

5 . The device according to claim 1 , wherein the second conductor pattern defines an array of gate conductors, providing the gate electrode for a respective column of the array of transistors, and extending also over the second insulator pattern.

6 . The device according to claim 5 , wherein the gate conductors adhere better to the surface of the second insulator pattern than to the surface of the first insulator pattern.

7 . The device according to claim 5 , wherein a semiconductor pattern provides the semiconductor channels, and the semiconductor pattern matches the first insulator pattern.

8 . A method comprising: forming a first conductor pattern; forming at least two insulator patterns over the first conductor pattern; forming a second conductor pattern over the at least two insulator patterns; wherein a first insulator pattern of the at least two insulator patterns occupies at least one or more semiconductor channel regions to provide a dielectric between one or more semiconductor channels and one or more conductors of one of the first and second conductor patterns; and wherein the method comprises forming a second insulator pattern of the at least two insulator patterns after forming the first insulator pattern, wherein the second insulator pattern defines windows in at least the one or more semiconductor channel regions through which the second conductor pattern contacts the first insulator pattern other than via the second insulator pattern.

9 . The method according to claim 8 , comprising providing a third conductor pattern selectively over the first insulator pattern, and wherein the second conductor pattern is formed over the first insulator pattern via the third conductor pattern, and contacts the first insulator pattern via the third conductor pattern.

10 . The method according to claim 9 , wherein the second insulator pattern overlaps the first insulator pattern outside the one or more semiconductor channel regions.

11 . The method according to claim 9 , wherein the first insulator pattern provides a dielectric between the one or more semiconductor channels and one or more conductors of the second conductor pattern, and the one or more conductors of the second level conductor pattern is formed at least over the whole area of the first insulator pattern.

12 . The method according to claim 11 , wherein forming the second conductor pattern comprises patterning one or more conductor layers in situ on the surface defined together by the at least two insulator patterns using one or more patterning agents; wherein the second insulator pattern comprises an insulator material that is less susceptible than one or more insulator materials constituting the first insulator pattern to surface roughening by the one or more patterning agents and/or less permeable than one or more insulator materials constituting the first insulator pattern to the one or more patterning agents.

13 . The method according to claim 9 , wherein the one or more windows extend over at least the whole area of the respective semiconductor channel regions.

14 . The method according to claim 9 , wherein the first insulator pattern comprises a stack of insulator layers.

15 . The method according to claim 9 , wherein the second conductor pattern defines an array of gate conductors, providing the gate electrodes for respective columns of the array of transistors, and extending also over the second insulator pattern.

16 . The method according to claim 15 , wherein the gate conductors exhibit better adhesion to the surface of the second insulator pattern than to the surface of the first insulator pattern.

17 . The method according to claim 15 , comprising forming a semiconductor pattern over the first conductor pattern to provide the semiconductor channels, and wherein the semiconductor pattern matches the first insulator pattern.

18 . A device comprising a stack of layers defining one or more electronic elements, wherein the stack comprises at least:
one or more semiconductor channels; a dielectric; a first conductor pattern defining one or more coupling conductors, wherein the one or more coupling conductors are capacitively coupled to the one or one or more semiconductor channels via the dielectric; a planarisation layer; a second conductor pattern defining one or more routing conductors, wherein the second conductor pattern is in contact with the first conductor pattern via through holes in at least the planarisation layer.

19 . The device according to claim 18 , wherein the second conductor pattern comprises an etched routing conductor layer.

Assignees

• Flexenable Ltd

Inventors

• Jongman Jan
• Dury Joffrey

Classifications

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W70/685 Primary

  comprising multiple insulating layers · CPC title

• H10D86/451 Primary

  characterised by the compositions or shapes of the interlayer dielectrics · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title