Memory device and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-2020395530-A1
Application number	US-201916443772-A
Country	US
Kind code	A1
Filing date	Jun 17, 2019
Priority date	Jun 17, 2019
Publication date	Dec 17, 2020
Grant date	—

Abstract

A magnetoresistive memory device includes a memory stack, a spin-orbit-torque (SOT) layer, and a free layer. The memory stack includes a pinned layer and a reference layer over the pinned layer. The SOT layer is spaced apart from the memory stack. The free layer is over the memory stack and the SOT layer.

First claim

1 . A magnetoresistive memory device comprising:
a memory stack comprising:
a pinned layer; and
a reference layer over the pinned layer;
a spin-orbit-torque (SOT) layer spaced apart from the memory stack; and a free layer over the memory stack and the SOT layer.

2 . The magnetoresistive memory device of claim 1 , further comprising a capping layer over the free layer.

3 . The magnetoresistive memory device of claim 2 , wherein perpendicular magnetic anisotropy is formed at an interface of the free layer and the capping layer.

4 . The magnetoresistive memory device of claim 2 , wherein the capping layer overlaps the SOT layer.

5 . The magnetoresistive memory device of claim 1 , wherein the free layer and the SOT layer extend toward different directions.

6 . The magnetoresistive memory device of claim 1 , wherein the memory stack further comprises a first electrode, and the pinned layer and the reference layer are over the first electrode.

7 . The magnetoresistive memory device of claim 6 , wherein the memory stack further comprises a seed layer between the first electrode and the pinned layer.

8 . The magnetoresistive memory device of claim 1 , further comprising:
a second electrode over the SOT layer; a first top via over the second electrode; a bit line over the SOT layer and connected to the second electrode through the first top via; and a third electrode over the SOT layer.

9 . The magnetoresistive memory device of claim 8 , wherein the second electrode and the third electrode are on opposite sides of the free layer.

10 . The magnetoresistive memory device of claim 1 , wherein the memory stack further comprises a tunnel barrier layer between the reference layer and the free layer.

11 . A magnetoresistive memory device, comprising:
a memory stack comprising:
a reference layer; and
a tunnel barrier layer over the reference layer;
a spin-orbit-torque (SOT) layer; a free layer in contact with a top surface of the tunnel barrier layer and the SOT layer; and a capping layer over the free layer, wherein the free layer is between the tunnel barrier layer and the capping layer.

12 . The magnetoresistive memory device of claim 11 , wherein the memory stack further comprises a pinned layer, and the reference layer is between the pinned layer and the tunnel barrier layer.

13 . The magnetoresistive memory device of claim 11 , wherein the tunnel barrier layer and the capping layer are made of the same material.

14 . The magnetoresistive memory device of claim 11 , further comprising a second electrode and a third electrode in contact with the SOT layer and on opposite sides of the capping layer.

15 . The magnetoresistive memory device of claim 14 , further comprising:
a first top via and a second top via respectively over the second electrode and the third electrode; and a bit line connected to the first top via.

16 . A method for manufacturing a magnetoresistive memory device comprising:
forming a memory stack; forming a dielectric layer covering the memory stack; forming a spin-orbit-torque (SOT) layer in the dielectric layer and spaced apart from the memory stack; removing a portion of the dielectric layer to expose the memory stack; and forming a free layer over the memory stack and the SOT layer.

17 . The method of claim 16 , further comprising forming a capping layer over the free layer.

18 . The method of claim 16 , wherein forming the memory stack comprises:
forming a conductive layer; forming a seed layer over the conductive layer; forming a pinned layer over the seed layer; forming a spacer layer over the pinned layer; forming a reference layer over the spacer layer; forming a tunnel barrier layer over the reference layer; and patterning the tunnel barrier layer, the reference layer, the spacer layer, the pinned layer, the seed layer, and the conductive layer to form the memory stack.

19 . The method of claim 16 , further comprising forming a first electrode and a second electrode over the SOT layer and on opposite sides of the free layer.

20 . The method of claim 19 , further comprising:
forming a first top via and a second top via respectively over the first electrode and the second electrode; and forming a bit line over the first electrode and connected to the first top via.

Assignees

• Taiwan Semiconductor Mfg Co Ltd
• Univ Nat Taiwan

Inventors

• Tsou Ya-Jui
• Luo zong-you
• Liu Chee-Wee
• Lin Shao-Yu
• Chung Liang-Chor
• Wang Chih-Lin

Classifications

• G11C11/1673

  Reading or sensing circuits or methods · CPC title

• G11C11/161 Primary

  details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell · CPC title

• G11C11/18

  using Hall-effect devices · CPC title

• G11C11/1675

  Writing or programming circuits or methods · CPC title

• H01L43/02 Primary

  Electricity · mapped topic