Strongarm latch comparator and method

Patent metadata

Field	Value
Publication number	US-2020389160-A1
Application number	US-201816492341-A
Country	US
Kind code	A1
Filing date	Jan 17, 2018
Priority date	May 2, 2017
Publication date	Dec 10, 2020
Grant date	—

Abstract

A StrongARM latch comparator (500) includes first and second p-type metal-oxide-semiconductor, PMOS, cross-coupled transistors (T1, T2); third and fourth n-type metal-oxide-semiconductor, NMOS, cross-coupled transistors (T3, T4), wherein the first PMOS cross-coupled transistor (T1) has a gate electrically coupled to a gate of the third NMOS cross-coupled transistor (T3) and the second PMOS cross-coupled transistor (T2) has a gate electrically coupled to a gate of the fourth NMOS cross-coupled transistor (T4); and fifth and sixth input transistors (T5, T6). The fifth input transistor (T5) is electrically connected between the first PMOS cross-coupled transistor (T1) and the third NMOS cross-coupled transistor (T3), and the sixth input transistor (T6) is electrically connected between the second PMOS cross-coupled transistor (T2) and the fourth NMOS cross-coupled transistor (T4).

First claim

1 . A StrongARM latch comparator comprising:
first and second p-type metal-oxide-semiconductor, PMOS, cross-coupled transistors (T 1 , T 2 ); third and fourth n-type metal-oxide-semiconductor, NMOS, cross-coupled transistors (T 3 , T 4 ), wherein the first PMOS cross-coupled transistor (T 1 ) has a gate electrically coupled to a gate of the third NMOS cross-coupled transistor (T 3 ) and the second PMOS cross-coupled transistor (T 2 ) has a gate electrically coupled to a gate of the fourth NMOS cross-coupled transistor (T 4 ); and fifth and sixth input transistors (T 5 , T 6 ), wherein the fifth input transistor (T 5 ) is electrically connected between the first PMOS cross-coupled transistor (T 1 ) and the third NMOS cross-coupled transistor (T 3 ), and the sixth input transistor (T 6 ) is electrically connected between the second PMOS cross-coupled transistor (T 2 ) and the fourth NMOS cross-coupled transistor (T 4 ).

2 . The latch comparator of claim 1 , further comprising:
a first charging transistor (CT 1 ) connected to the first cross-coupled transistor (T 1 ) so that their sources are connected to each other and their drains are connected to each other; and a second charging transistor (CT 2 ) connected to the second cross-coupled transistor (T 2 ) so that their sources are connected to each other and their drains are connected to each other.

3 . The latch comparator of claim 2 , further comprising:
a tail current transistor (T 7 ) connected to the third and fourth cross-coupled transistors (T 3 , T 4 ).

4 . The latch comparator of claim 3 , further comprising:
a first inverter (I 1 ) connected to a first node A; and a second inverter (I 2 ) connected to a second node A′.

5 . The latch comparator of claim 4 , wherein a source of the first cross-coupled transistor (T 1 ), a source of the first charging transistor (CT 1 ), a source of the second cross-coupled transistor (T 2 ), and a source of the second charging transistor (CT 2 ) are coupled to a drain voltage V dd .

6 . The latch comparator of claim 5 , wherein a drain of the first cross-coupled transistor (T 1 ) and a drain of the fifth input transistor (T 5 ) are electrically connected to the first node A, and a drain of the second cross-coupled transistor (T 2 ) and a drain of the sixth input transistor (T 6 ) are electrically connected to the second node A′.

7 . The latch comparator of claim 6 , wherein a source of the fifth input transistor (T 5 ) is electrically connected to a drain of the third cross-coupled transistor (T 3 ) and a source of the sixth input transistor (T 6 ) is electrically connected to a drain of the fourth cross-coupled transistor (T 4 ).

8 . The latch comparator of claim 7 , wherein a source of the third cross-coupled transistor (T 3 ) and a source of fourth cross-coupled transistor (T 4 ) are directly connected to a drain of the tail current transistor (T 7 ), and a source of the tail current transistor (T 7 ) is connected to ground.

9 . The latch comparator of claim 8 , wherein a gate of the first charging transistor (CT 1 ), a gate of the second charging transistor (CT 2 ) and a gate of the tail current transistor (T 7 ) are connected to a same clock signal.

10 . A method for driving a StrongARM latch comparator, the method comprising:
applying a voltage V DD to the sources of the first and second PMOS cross-coupled transistors (T 1 , T 2 ); applying a ground voltage V 0 to a tail current transistor (T 7 ), wherein third and fourth NMOS cross-coupled transistors (T 3 , T 4 ) are connected to the tail current transistor, and wherein the first PMOS cross-coupled transistor (T 1 ) has a gate electrically coupled to a gate of the third NMOS cross-coupled transistor (T 3 ) and the second PMOS cross-coupled transistor (T 2 ) has a gate electrically coupled to a gate of the fourth NMOS cross-coupled transistor (T 4 ); and applying a common mode voltage to a fifth input transistor (T 5 ) and applying the common mode voltage and a small differential voltage to a sixth input transistor (T 6 ), wherein the fifth input transistor (T 5 ) is electrically connected between the first PMOS cross-coupled transistor (T 1 ) and the third NMOS cross-coupled transistor (T 3 ), and the sixth input transistor (T 6 ) is electrically connected between the second PMOS cross-coupled transistor (T 2 ) and the fourth NMOS cross-coupled transistor (T 4 ).

11 . The method of claim 10 , wherein
a first charging transistor (CT 1 ) is connected to the first cross-coupled transistor (T 1 ) so that their sources are connected to each other and their drains are connected to each other; and a second charging transistor (CT 2 ) is connected to the second cross-coupled transistor (T 2 ) so that their sources are connected to each other and their drains are connected to each other.

12 . The method of claim 11 , wherein a drain of the tail current transistor (T 7 ) is connected to a source of each of the third and fourth cross-coupled transistors (T 3 , T 4 ).

13 . The method of claim 12 , further comprising:
outputting a first output voltage VA n from a first inverter (I 1 ) connected to a first node A; and outputting a second output voltage VA n from a second inverter (I 2 ) connected to a second node A′.

14 . The method of claim 13 , further comprising:
applying a voltage V DD to a source of the first cross-coupled transistor (T 1 ), a source of the first charging transistor (CT 1 ), a source of the second cross-coupled transistor (T 2 ), and a source of the second charging transistor (CT 2 ).

15 . The method of claim 14 , wherein a drain of the first cross-coupled transistor (T 1 ) and a drain of the fifth input transistor (T 5 ) are electrically connected to the first node A, and a drain of the second cross-coupled transistor (T 2 ) and a drain of the sixth input transistor (T 6 ) are electrically connected to the second node A′.

16 . The method of claim 15 , wherein a source of the fifth input transistor (T 5 ) is electrically connected to a drain of the third cross-coupled transistor (T 3 ) and a source of the sixth input transistor (T 6 ) is electrically connected to a drain of the fourth cross-coupled transistor (T 4 ).

17 . The method of claim 16 , wherein a source of the third cross-coupled transistor (T 3 ) and a source of fourth cross-coupled transistor (T 4 ) are directly connected to a drain of the tail current transistor (T 7 ), and a source of the tail current transistor (T 7 ) is connected to the ground.

18 . The method of claim 11 , further comprising:
applying a clock signal to a gate of the first charging transistor (CT 1 ), a gate of the second charging transistor (CT 2 ) and a gate of the tail current transistor (T 7 ).

19 . A circuit comprising:
first to fourth cross-coupled transistors (T 1 , T 2 , T 3 , T 4 ), wherein the first cross-coupled transistor (T 1 ) has a gate electrically coupled to a gate of the third cross-coupled transistor (T 3 ) and the second cross-coupled transistor (T 2 ) has a gate electrically coupled to a gate of the fourth cross-coupled transistor (T 4 ); and fifth and sixth input transistors (T 5 , T 6 ), wherein the fifth input transistor (T 5 ) is directly, electrically, connected to the first cross-coupled transistor (T 1 ) and to the third cross-coupled transistor (T 3 ) and the sixth input transistor (T 6 ) is directly, electrically, connected to the second cross-coupled transistor (T 2 ) and the fourth cross-coupled transistor (T 4 ).

20 . The circuit of claim 19 ,

Assignees

• Univ King Abdullah Sci & Tech

Inventors

• Almansouri Abdullah Saud
• Alturki Abdullah Turki
• Al-Attar Talal

Classifications

• H03K5/249

  using clock signals · CPC title

• H03K5/2481 Primary

  with at least one differential stage · CPC title

• H03K17/6872

  using complementary field-effect transistors · CPC title