Display devices

Patent metadata

Field	Value
Publication number	US-2020388659-A1
Application number	US-201816764521-A
Country	US
Kind code	A1
Filing date	Nov 12, 2018
Priority date	Nov 17, 2017
Publication date	Dec 10, 2020
Grant date	—

Abstract

A technique comprising: providing a workpiece including a stack of layers defining an array of transistors including organic semiconductor channels, wherein the stack of layers comprises an upper conductor pattern ( 8 ) defining an array of upper conductor elements, each in contact with a respective lower conductor element ( 6 ) of a lower conductor pattern in via-hole regions ( 10 ); the method comprising: processing the workpiece by forming over the upper conductor pattern a plugging layer that raises the upper surface level of the workpiece in at least the via-hole regions whilst leaving at least a portion of each upper conductor element exposed; and providing an optical medium ( 36 ) over the upper conductor pattern without first forming an inorganic moisture barrier layer on the upper surface of the workpiece.

First claim

1 . A method comprising: providing a workpiece including a stack of layers defining an array of transistors including organic semiconductor channels, wherein the stack of layers comprises an upper conductor pattern defining an array of upper conductor elements, each in contact with a respective lower conductor element of a lower conductor pattern in via-hole regions; the method comprising: processing the workpiece by forming over the upper conductor pattern a plugging layer that raises the upper surface level of the workpiece in at least the via-hole regions whilst leaving at least a portion of each upper conductor element exposed; and providing an optical medium over the upper conductor pattern without first forming an inorganic moisture barrier layer on the upper surface of the workpiece.

2 . The method according to claim 1 , wherein the upper surface of the plugging layer is no lower than the upper surface of the upper conductor pattern outside the via-hole regions.

3 . The method according to claim 1 , wherein the optical medium comprises a liquid crystal material, and the method comprises forming an alignment layer on the upper surface of the workpiece over the upper conductor pattern without first forming an inorganic moisture barrier layer over the upper surface of the workpiece.

4 . The method according to claim 1 , wherein the optical medium comprises a light-emitting diode comprising an organic light-emitting material, and the method comprises forming an element of the light-emitting diode over the upper surface of the workpiece without first forming an inorganic moisture barrier layer over the upper surface of the workpiece.

5 . The method according to claim 1 , wherein forming the plugging layer comprises forming a planarization layer over the upper surface of the work piece, and then patterning the planarization layer to expose at least a portion of each of the upper conductive elements.

6 . The method according to claim 5 , comprising forming a further conductor pattern over the planarization layer, the further conductor pattern defining an array of further conductive elements each in contact with a respective one of the upper conductive elements, wherein the area occupied by each further conductive element includes the via-hole region in which the respective upper conductive element contacts the respective lower conductive element.

7 . A display device, comprising: a stack of layers defining an array of transistors including organic semiconductor channels, wherein the stack of layers comprises an upper conductor pattern defining an array of upper conductor elements, each in contact with a respective lower conductive element of a lower conductor pattern in a respective via-hole region; a patterned planarization layer that extends at least to the upper surface of the upper conductor pattern in the via-hole regions, and leaves at least a portion of each upper conductive element exposed; and an optical medium over the upper conductor pattern without any inorganic moisture barrier layer between the upper conductor pattern and the optical medium.

8 . The display device according to claim 7 , wherein the optical medium comprises a liquid crystal material, and device comprises an alignment layer over the upper conductor pattern without any inorganic moisture barrier layer between the upper conductor pattern and the alignment layer.

9 . The display device according to claim 7 , wherein the optical medium comprises a light-emitting diode comprising an organic light-emitting material, and the display device comprises an element of the light-emitting diode over the upper conductor pattern without any inorganic moisture barrier layer between the upper conductor pattern and the element of the light-emitting diode.

10 . The display device according to claim 9 , comprising a further conductor pattern over the patterned planarization layer, the further conductor pattern defining an array of further conductive elements each in contact with a respective one of the upper conductive elements; wherein the area occupied by each further conductive element includes the via-hole region in which the respective upper conductive element contacts the respective lower conductive element.

11 . The method according to claim 1 , wherein forming the plugging layer comprises forming a planarisation layer over the upper conductor pattern, wherein the planarisation layer has a planar upper surface at a level no lower than the upper surface of the upper conductor pattern; and patterning the planarisation layer so as to expose the upper conductor elements outside the via-hole regions; wherein, after the patterning, the upper surface of the planarisation layer in the via-hole regions is at a level lower than the upper surface of the conductor pattern outside the via-regions.

12 . The method according to claim 1 , further comprising: forming banks to define wells, wherein the wells occupy areas including at least the via-hole regions.

13 . The method according to claim 2 , further comprising: depositing light-emitting material into the wells.

14 . The device according to claim 7 , further comprising: banks defining wells, wherein the wells occupy areas including at least the via-hole regions.

15 . The method according to claim 7 , further comprising: light-emitting material in the wells.

16 . A display device, comprising: a stack of layers defining an array of transistors including organic semiconductor channels, wherein the stack of layers comprises an upper conductor pattern defining an array of upper conductor elements, each in contact with a respective lower conductive element of a lower conductor pattern in a respective via-hole region; a patterned planarization layer occupying at least the whole area of the via-hole regions, wherein the patterned planarisation layer is over the lower conductor pattern in the via-hole regions, and has an upper surface at a level lower than the level of the upper surface of the upper conductor pattern outside the via-regions; and wherein the device further comprises an optical medium over the upper conductor pattern without any inorganic moisture barrier layer between the upper conductor pattern and the optical medium.

17 . The device according to claim 16 , wherein the level of the upper surface of the patterned planarisation layer is higher than the level of the interface outside the via-hole regions between the upper conductor pattern and an underlying layer.

Assignees

• Flexenable Ltd

Inventors

• Harrison Charlotte
• Norval Shane

Classifications

• H10D86/021

  of multiple TFTs · CPC title

• G02F1/1368

  in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)} · CPC title

• G02F2202/022

  polymeric · CPC title

• G02F1/136227 Primary

  Through-hole connection of the pixel electrode to the active element through an insulation layer · CPC title

• H01L27/3248 Primary

  Electricity · mapped topic