Semiconductor package substrate, method for fabricating the same, and electronic package having the same

Patent metadata

Field	Value
Publication number	US-2020388564-A1
Application number	US-202016897372-A
Country	US
Kind code	A1
Filing date	Jun 10, 2020
Priority date	Jun 10, 2019
Publication date	Dec 10, 2020
Grant date	—

Abstract

A semiconductor package substrate, a method for fabricating the same, and an electronic package having the same are provided. The method includes: providing a circuit structure having a first solder pad and a second solder pad; forming on the circuit structure a metal sheet having a first hole, from which the first solder pad is exposed, and a second hole, from which the second solder pad is exposed; and forming an insulation layer on the metal sheet and a hole wall of the second hole. A first conductive element that is to be grounded is disposed in the first hole and is in contact with the metal sheet and the first solder pad. Therefore, heat generated in a signal transmission process is dissipated by the metal sheet and the first conductive element.

First claim

What is claimed is:

1 . A semiconductor package substrate, comprising:
a circuit structure having a chip mounting side and a ball planting side opposing the chip mounting side, the circuit structure comprising:
at least one dielectric layer; and
a circuit layer formed on the dielectric layer,
wherein the circuit layer on the ball planting side includes a plurality of first solder pads and a plurality of second solder pads;
a metal sheet having a plurality of first holes for the first solder pads to be exposed therefrom, and a plurality of second holes for the second solder pads to be exposed therefrom; a bonding material bonding the metal sheet onto the ball planting side of the circuit structure; and an insulation layer formed on the metal sheet and a hole wall of each of the second holes, and being free from being formed on a hole wall of each of the first holes.

2 . The semiconductor package substrate of claim 1 , further comprising a plurality of first conductive elements bonded onto the first solder pads in the first holes and being in contact with the metal sheet.

3 . The semiconductor package substrate of claim 1 , further comprising a plurality of second conductive elements bonded onto the second solder pads in the second holes and being in contact with the insulation layer and in no contact with the metal sheet.

4 . An electronic package, comprising:
the semiconductor package substrate of claim 1 ; and at least an electronic component disposed on the chip mounting side of the circuit structure.

5 . The electronic package of claim 4 , further comprising a plurality of first conductive elements bonded onto the first solder pads in the first holes and being in contact with the metal sheet.

6 . The electronic package of claim 4 , further comprising a plurality of second conductive elements bonded onto the second solder pads in the second holes and being in contact with the insulation layer and in no contact with the metal sheet.

7 . The electronic package of claim 4 , further comprising an encapsulation layer formed on the semiconductor package substrate and bonding the electronic component onto the semiconductor package substrate.

8 . The electronic package of claim 4 , further comprising a plurality of conductive bumps, wherein the electronic component is disposed on the chip mounting side of the circuit structure via the conductive bumps.

9 . A method for fabricating a semiconductor package substrate, comprising:
providing a circuit structure having a chip mounting side and a ball planting side opposing the chip mounting side, wherein the circuit structure comprises:
at least one dielectric layer;
a circuit layer formed on the dielectric layer; and
a plurality of first solder pads and a plurality of second solder pads disposed on the circuit layer on the ball planting side;
bonding a metal sheet onto the ball planting side of the circuit structure via a bonding material; forming on the metal sheet a plurality of first holes for the first solder pads to be exposed therefrom, and a plurality of second holes for the second solder pads to be exposed therefrom; forming an insulation layer on the ball planting side of the circuit structure and the metal sheet; and removing a portion of the insulation layer on the first solder pads in the first holes and the second solder pads in the second holes, with the first and second solder pads exposed from the first and second holes, respectively, and the insulation layer remained on a hole wall of each of the second holes.

10 . The method of claim 9 , further comprising disposing on the first solder pads in the first holes a plurality of first conductive elements in contact with the metal sheet.

11 . The method of claim 9 , further comprising disposing on the second solder pads in the second holes a plurality of second conductive elements in contact with the insulation layer and in no contact with the metal sheet.

12 . The method of claim 9 , further comprising disposing a plurality of conductive bumps on the chip mounting side of the circuit structure, and bonding the conductive bumps to an electronic component.

Assignees

• Phoenix Pioneer Technology Co Ltd

Inventors

• Chou Pao-Hung
• Yu Chun-Hsien
• Hsu Shih-Ping

Classifications

• H10W70/687

  characterized by the outer layers being for protection, e.g. solder masks, or for protection against chemical or mechanical damage · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/252

  comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title