Power Switch Multiplexer with Configurable Overlap

Patent metadata

Field	Value
Publication number	US-2020387205-A1
Application number	US-201916433801-A
Country	US
Kind code	A1
Filing date	Jun 6, 2019
Priority date	Jun 6, 2019
Publication date	Dec 10, 2020
Grant date	—

Abstract

A power switch multiplexer with configurable overlap is disclosed. An integrated circuit (IC) includes a first functional circuit block coupled to receive a supply voltage from a first supply voltage node. The IC further includes an input circuit and an output circuit. Responsive to receiving an input signal, the input circuit asserts an activation signal to cause one of a second supply voltage node and a third supply voltage node to be electrically coupled to the first supply voltage node. Subsequently the input circuit asserts a deactivation signal to cause the other one of the second and third supply voltage nodes to be electrically decoupled from the first supply voltage node. The output circuit is coupled to receive the activation signal and the deactivation signal, and configured to assert a first output signal subsequent to receiving the activation signal.

First claim

1 . An integrated circuit comprising:
a first functional circuit block coupled to receive a supply voltage from a first supply voltage node; and a first power switch network comprising:
a first input circuit configured to, responsive to receiving a first input signal, assert a first activation signal to cause one of a second supply voltage node and a third supply voltage node to be electrically coupled to the first supply voltage node and subsequently assert a first deactivation signal to cause the other one of the second and third supply voltage nodes to be electrically decoupled from the first supply voltage node; and
a first output circuit coupled to receive the first activation signal and the first deactivation signal, and configured to:
during operation in a first mode, assert a first output signal to a first logic level from a second, different logic level, responsive to receiving the first activation signal and prior to receiving the first deactivation signal at a logic level eguivalent to that of the first activation signal; and
during operation in a second mode, assert the first output signal from the first logic level to the second logic level responsive to receiving both the first activation signal and the first deactivation signal at equivalent logic levels; and

a second power switch network having a second input circuit, wherein the second input circuit is configured to assert a second activation signal responsive to the first output circuit asserting the first output signal to the first logic level.

2 . The integrated circuit as recited in claim 1 , further comprising a first plurality of power switches coupled between the second supply voltage node and the first supply voltage node and a second plurality of power switches coupled between the third supply voltage node and the first supply voltage node.

3 . The integrated circuit as recited in claim 2 , wherein power switches of ones the first and second plurality of power switches are arranged to be sequentially activated responsive to receiving the activation signal and to be sequentially deactivated responsive to receiving the deactivation signal.

4 . The integrated circuit as recited in claim 1 , wherein the first input circuit is configured to assert the deactivation signal responsive to completion of coupling of the one of the second and third supply voltage nodes to the first supply voltage node.

5 . The integrated circuit as recited in claim 1 , wherein the first output circuit is configured to assert the first output signal responsive to receiving the activation signal and prior to receiving the deactivation signal.

6 . The integrated circuit as recited in claim 1 , wherein the first output circuit is configured to assert the first output signal responsive to receiving the deactivation signal, wherein the deactivation signal is received subsequent to receiving the activation signal.

7 . The integrated circuit as recited in claim 1 , wherein the first output circuit is coupled to receive the activation signal responsive to completing of electrically coupling of one of the second and third supply voltage nodes to the first supply voltage node, and further coupled to receive the deactivation signal responsive to decoupling of the other one of the second and third supply voltage nodes from the first supply voltage node.

8 . The integrated circuit as recited in claim 1 , wherein the output circuit is configured to operate in a third mode responsive to receiving a bypass signal from the input circuit, and wherein, when operating in the third mode:
the first input circuit is configured to assert the bypass signal responsive to receiving the input signal; and the fir output circuit is configured to assert the output signal responsive to receiving the bypass signal from the input circuit.

9 . The integrated circuit as recited in claim 1 , wherein the input circuit is further configured to cause the functional circuit block to operate in a fourth mode, wherein, during operation in the fourth mode, the input circuit is configured to cause the second and third supply voltage nodes to be electrically decoupled form the first supply voltage node.

10 . The integrated circuit as recited in claim 1 , further comprising:
a second functional circuit block coupled to receive a supply voltage from a fourth supply voltage node, wherein the second input circuit of the second power switch includes:
an input coupled to receive, as a second input signal, the first output signal from the first output circuit, wherein the second input circuit is configured to assert the second activation signal to couple one of the second and third supply voltage nodes to the fourth supply voltage node, and further configured to assert a second deactivation signal to decouple the other one of the second and third supply voltage nodes from the fourth supply voltage node; and
a second output circuit coupled to receive the second activation signal and the second deactivation signal, and configured to assert a second output signal subsequent to receiving the second activation signal; and
a power management circuit coupled to provide mode control signals to ones of the first and second power switch networks, wherein the ones of the first and second power switch networks are configured to operate in one of a plurality of operational modes based on respectively received mode control signals.

11 . A method comprising:
providing power to a first functional circuit block from a first supply voltage node via one of a second supply voltage node and a third supply voltage node; changing a state of a first input signal provided to a first input circuit to a second logic level from a first logic level; asserting by the first input circuit, a first activation signal responsive to the changing of the state of the first input signal; electrically coupling a previously unselected one of the second and third supply voltage nodes to the first supply voltage node responsive to asserting the first activation signal; asserting by the first input circuit, a first deactivation signal responsive to electrically coupling the previously unselected one of the second and third supply voltage nodes; electrically decoupling a previously selected one of the second and third supply voltage nodes from the first supply voltage node responsive to asserting the first deactivation signal; asserting, to the first logic level by a first output circuit, a first output signal subsequent to completing electrically coupling the previously unselected one of the second and third supply voltage nodes, wherein during operation in a first mode, the first output signal is asserted responsive to receiving the first activation signal and prior to receiving the first deactivation signal at a logic level eguivalent to that of the first activation signal, and during operation in a second mode, the output signal is asserted responsive to receiving both the first activation signal and the first deactivation signal at equivalent logic levels; and asserting, by a second input circuit, a second activation signal to the first logic level responsive to the first output circuit asserting the first output signal to the first logic level.

12 . The method as recited in claim 11 , further comprising the first output circuit asserting the first output signal responsive to completing both electrically coupling the previously unselected one of the second and third supply voltage nodes to the first supply voltage node and decoupling the previously selected one of the second and third supply voltage nodes from the first supply voltage node.

13 . The method as recited in claim

Assignees

• Apple Inc

Inventors

• Zyuban Victor
• Hess Greg M
• Gajjewar Hemangi U

Classifications

• H03K17/122

  in field-effect transistor switches · CPC title

• G06F1/263 Primary

  Arrangements for using multiple switchable power supplies, e.g. battery and AC (G06F1/30 takes precedence) · CPC title

• H03K19/0016

  by using a control or a clock signal, e.g. in order to apply power supply · CPC title

• H03K19/1733 Primary

  Controllable logic circuits (H03K19/177 takes precedence) · CPC title

• H03K17/223

  in field-effect transistor switches · CPC title