Systems and methods for calibrating devices using directed acyclic graphs

Patent metadata

Field	Value
Publication number	US-2020379768-A1
Application number	US-202016854396-A
Country	US
Kind code	A1
Filing date	Apr 21, 2020
Priority date	May 3, 2019
Publication date	Dec 3, 2020
Grant date	—

Abstract

A hybrid processor includes a classical (digital) processor and a quantum processor and implements a calibration procedure to calibrate devices in the quantum processor. Parameter measurements are defined as vertices in a directed acyclic graph. Dependencies between measurements are defined as directed edges between vertices. The calibration procedure orders the vertices, respecting the order of the dependencies while at least attempting to reduce the time needed to perform all the measurements. The calibration procedure provides a level of abstraction to allow non-expert users to use the calibration procedure. Each vertex has a set of attributes defining the status of the measurement, time of the measurement and value of the measurement.

First claim

1 . A method of operation of a hybrid processor, the hybrid processor comprising a quantum processor and a classical processor, the quantum processor having a plurality of devices, each of the plurality of devices having at least one respective parameter such that the quantum processor has a set of parameters comprising the at least one respective parameter of each of the plurality of devices, at least one of the parameters in the set of parameters having a dependence from another one of the parameters in the set of parameters, the method comprising:
mapping the set of parameters as a plurality of vertices in a graph via the classical processor; mapping each of the dependencies between parameters in the set of parameters as directed edges in the graph via the classical processor; ordering the vertices of the graph via the classical processor; and measuring each parameter in the set of parameters according to the order of the vertices of the graph via the classical processor.

2 . The method of claim 1 wherein ordering the vertices of the graph includes ordering the vertices of the graph using one of: a topological sort, a breadth-first sort, a depth-first sort, and a best-first sort.

3 . The method of claim 1 wherein mapping the set of parameters as a plurality of vertices in a graph includes mapping a vertex for each parameter whose measurement value is used to operate the quantum processor.

4 . The method of claim 3 wherein mapping a vertex for each parameter includes mapping a vertex having a time, a status, and at least one value.

5 . The method of claim 4 wherein mapping a vertex having a time, a status, and at least one value includes mapping a vertex having a time comprising the time the vertex was given a status.

6 . The method of claim 4 further comprising updating the graph by at least one of: changing edges, adding edges, removing edges, adding vertices, removing vertices, updating vertices.

7 . The method of claim 6 wherein updating the graph comprises updating the graph by updating vertices, and updating vertices includes updating the time, the status, and the at least one value.

8 . The method of claim 6 wherein updating the graph includes updating the graph in response to an error.

9 . The method of claim 6 wherein measuring each parameter in the set of parameters further comprises interrupting measuring a selected parameter after a threshold time.

10 . The method of claim 9 wherein interrupting the measuring a parameter after a threshold time includes saving any intermediate measurement of the parameter in a memory system.

11 . The method of claim 1 wherein mapping each of the dependencies between parameters in the set of parameters as directed edges in the graph comprises mapping dependencies including at least one of: a vertex dependent on more than one other vertex, a vertex dependent on a subset of other vertices, a vertex dependent on the value of another vertex being unchanged, a vertex dependent on having measured the value of another vertex, and a vertex dependent on the time of another vertex being unchanged.

12 . The method of claim 1 further comprising running a set of diagnostics on the plurality of devices via the classical processor; and
in response to at least one respective device parameter having a parameter value different from a previously measured parameter value, measuring the at least one respective device parameter according to the order of the vertices of the graph via the classical processor.

13 . The method of claim 12 wherein running a set of diagnostics on the plurality of devices includes running a set of diagnostics comprising one or more of: identifying trapped flux in couplers, identifying trapped flux in persistent current (Ip) compensators, identifying trapped flux in compound-compound Josephson junction (CCJJ) structures, identifying trapped flux in minor lobes, and identifying residual changes.

14 . A hybrid computational system, the hybrid computational system comprising a quantum processor and a classical processor, the quantum processor comprising a plurality of devices, each of the plurality of devices having at least one respective parameter such that the quantum processor has a set of parameters comprising the at least one respective parameter of each of the plurality of devices, at least one of the parameters in the set of parameters having a dependence from another one of the parameters in the set of parameters, the classical processor operable to:
map the set of parameters as a plurality of vertices in a graph;
map each of the dependencies between parameters in the set of parameters as directed edges in the graph;
order the vertices of the graph; and
measure each parameter in the set of parameters according to the order.

15 . The hybrid computational system of claim 14 wherein the classical processor is operable to order the vertices of the graph by one of: a topological sort, a breadth-first sort, a depth-first sort, and a best-first sort.

16 . The hybrid computational system of claim 14 wherein the classical processor is operable to map a vertex for each parameter needed to operate the quantum processor.

17 . The hybrid computational system of claim 14 wherein each vertex has a time, a status, and at least one value.

18 . The hybrid computational system of claim 15 wherein the time comprises the time a status was given to the vertex.

19 . The hybrid computation system of claim 15 wherein the classical processor is further operable to update edges, remove edges, add edges, add vertices, remove vertices, and update vertices.

20 . The hybrid computational system of claim 17 wherein the classical processor is operable to update the status, the time, and the at least one value of each vertex.

21 . The hybrid computational system of claim 17 wherein the classical processor is operable update the graph in response to an error.

22 . The hybrid computational system of claim 17 wherein the classical processor is operable to interrupt the measurement of a parameter after a threshold time.

23 . The hybrid computational system of claim 22 wherein the classical processor is operable to store any intermediate measurement of the parameter in a classical processor memory system.

24 . The hybrid computational system of claim 14 wherein the dependence between parameters in the set of parameters is defined as one of: a vertex dependent on more than one other vertex, a vertex dependent on a subset of other vertices, a vertex dependent on the value of another vertex being unchanged, a vertex dependent on having measured the value of another vertex, and a vertex dependent on the time of another vertex being unchanged.

Assignees

• D Wave Systems Inc

Inventors

• Berkley Andrew J
• Perminov Ilya V
• Johnson Mark W
• Rich Christopher B
• Altomare Fabio
• Lanting Trevor M

Classifications

• G06N10/40

  Physical realisations or architectures of quantum processors or components for manipulating qubits, e.g. qubit coupling or qubit control · CPC title

• G06F16/9024 Primary

  Graphs; Linked lists (G06F16/9027 takes precedence) · CPC title

• G06F9/3838 Primary

  Dependency mechanisms, e.g. register scoreboarding · CPC title

• H01L39/223

  Electricity · mapped topic

• G06N10/00

  Quantum computing, i.e. information processing based on quantum-mechanical phenomena · CPC title