Ps15 base current sampling in synchronous mode

Patent metadata

Field	Value
Publication number	US-2020373960-A1
Application number	US-202016991553-A
Country	US
Kind code	A1
Filing date	Aug 12, 2020
Priority date	Nov 27, 2018
Publication date	Nov 26, 2020
Grant date	—

Abstract

Multiple sensors are coupled to a first pin of a PSI5 transceiver to receive a sensor bus signal. A Manchester decoder is coupled to a second pin and a battery is coupled to a third pin. A comparator receives a first voltage that is proportional to a current on the sensor bus signal and a second voltage that is proportional to a base current on the sensor bus signal and sends a data output signal to the second pin. A sample-and-hold circuit captures a third voltage used to effect the second voltage responsive to a high value on a base current sampling signal. A base-current-renewal circuit detects edge transitions on the data output signal and when the data output signal has no edge transitions for a period of time greater than a gap time defined in a PSI5 standard, sets the base current sampling signal high.

First claim

What is claimed is:

1 . A transceiver comprising:
current sense circuitry having a sensor bus node adapted to provide a supply current, to supply a synchronous pulse at regular intervals, and to sense changes in the supply current representing sensor data during time slots, the current sense circuit having a supply current sense output; sample and hold circuitry having a supply current sense input coupled to the supply current sense output, having a base current sampling control input, and having a sampled output; comparison circuitry having an input coupled to the supply current sense input, having an input coupled to the sampled output, and having a data output; and base current renewal circuitry having an input coupled to the data output, having a sampling control input, and having a base current sampling output coupled to the base current sampling control input.

2 . The transceiver of claim 1 in which the base current renewal circuitry includes idle-time counting circuitry having an input coupled to the data output and having a timed sampling control output.

3 . The transceiver of claim 2 in which the base current renewal circuitry includes an OR circuit having a first input coupled to the sampling control input, a second input coupled to the timed sampling control output, and having an output coupled to the base current sampling output.

4 . The transceiver of claim 2 in which the base current renewal circuitry includes deglitch circuitry coupled between the data output and the idle time counting circuitry input.

5 . The transceiver of claim 1 in which the sample and hold circuitry includes a capacitor coupled to the sampled output, and a switch having an input coupled to the supply current sense input, having a control input coupled to the base current sampling control input, and having an output coupled to the capacitor.

6 . The transceiver of claim 1 in which the comparison circuitry is coupled between a medium voltage VDD-MV and a low voltage VDD-LV.

7 . The transceiver of claim 1 in which the current sense circuitry is coupled between a high voltage VDD-HV and a medium voltage VDD-MV.

8 . The transceiver of claim 1 including channel circuitry having an input coupled to the data output and having a channel output.

9 . The transceiver of claim 8 including decoder circuitry having an input coupled to the channel output and having a decoded output.

10 . The transceiver of claim 9 in which the decoder circuitry is Manchester decoder circuitry.

11 . A process comprising:
provide a supply current on a single wire; sending sync pulses at regular periods on the single wire; sensing changes in the supply current on the single wire, the supply current changes representing sensor data occurring during time slots between sync pulses, there being gap times between time slots, and the gap times being larger than a maximum bit duration before a next time slot begins; regularly sampling a base current on a capacitor at each sync pulse; and additionally sampling the base current on the capacitor after sensing no sensor data for a time greater than a gap time.

12 . The process of claim 11 in which the additionally sampling includes detecting edge transitions on the single wire.

13 . The process of claim 12 in which the additionally sampling includes deglitching edge transitions on the single wire.

14 . The process of claim 11 in which the additionally sampling includes counting clock cycles between edge transitions on the single wire.

15 . The process of claim 14 in which the additionally sampling includes setting an additional sampling signal when a count of clock cycles is greater than a number of clock cycles that represents a gap time.

16 . The process of claim 11 in which the additionally sampling includes setting an additional sampling signal to sample the base current level on the single wire.

17 . The process of claim 11 in which the regularly sampling includes setting a regular sampling signal to sample the base current level on the single wire.

18 . The process of claim 11 including setting a regular sampling signal or setting an additional sampling signal to sample the base current level on the single wire.

19 . The process of claim 11 in which the regular sampling includes regular sampling after each sync pulse.

20 . The process of claim 11 in which the sending includes sending sync pulses in periods greater than 500 microseconds.

Assignees

• Texas Instruments Inc

Inventors

• Easwaran Sri Navaneethakrishnan
• Lekan Ted F
• Zroka Michael J
• Rollman Darren J

Classifications

• B60T2220/04

  Pedal travel sensor, stroke sensor; Sensing brake request · CPC title

• G01R19/2509

  Details concerning sampling, digitizing or waveform capturing · CPC title

• G01R19/25

  using digital measurement techniques · CPC title

• H03K5/2472 Primary

  using field effect transistors (H03K5/2436 takes precedence) · CPC title

• H03K5/24

  the characteristic being amplitude · CPC title