Apparatus for determining a pass voltage of a read operation

Patent metadata

Field	Value
Publication number	US-2020372961-A1
Application number	US-202016990137-A
Country	US
Kind code	A1
Filing date	Aug 11, 2020
Priority date	Dec 28, 2018
Publication date	Nov 26, 2020
Grant date	—

Abstract

Apparatus having plurality of data lines each selectively connected to a respective string of series-connected memory cells, a plurality of registers each configured to indicate a state of a respective data line, and logic configured to indicate when each data line of the plurality of data lines has a particular state might facilitate determination of a pass voltage of a read operation.

First claim

What is claimed is:

1 . An apparatus, comprising:
an array of memory cells comprising a plurality of strings of series-connected memory cells; a plurality of access lines, each access line of the plurality of access lines connected to a respective memory cell of each string of series-connected memory cells of the plurality of strings of series-connected memory cells; a plurality of data lines, each data line of the plurality of data lines selectively connected to a respective string of series-connected memory cells of the plurality of strings of series-connected memory cells; a voltage generation system having an output selectively connected to an access line of the plurality of access lines; a plurality of sensing devices, each sensing device of the plurality of sensing devices connected to a respective data line of the plurality of data lines; a plurality of registers, each register of the plurality of registers configured to change from a first value to a second value responsive to an output of a respective sensing device of the plurality of sensing devices changing logic levels while the voltage generation system is increasing a voltage level at its output and while the output of the voltage generation system is connected to the access line; and a logic circuit configured to output a first logic level in response to each register of the plurality of registers having its second value and to output a second logic level, different than its first logic level, in response to any register of the plurality of registers having its first value; wherein the voltage generation system is configured to cease increasing the voltage level at its output in response to the logic circuit outputting its first logic level.

2 . The apparatus of claim 1 , wherein the voltage generation system of the apparatus comprises:
a counter; and a voltage generation circuit responsive to an output of the counter, and having an output selectively connected to the access line of the plurality of access lines; wherein the voltage generation system being configured to cease increasing the voltage level at its output in response to the logic circuit outputting its first logic level comprises the voltage generation system being configured to disable the counter in response to the logic circuit outputting its first logic level.

3 . The apparatus of claim 2 , wherein the voltage generation system being configured to cease increasing the voltage level at its output in response to the logic circuit outputting its first logic level comprises the voltage generation system being configured to cease increasing the voltage level at its output after a predetermined delay following the logic circuit outputting its first logic level.

4 . The apparatus of claim 2 , wherein the plurality of registers is a plurality of first registers, and wherein the apparatus further comprises:
a plurality of second registers, each second register of the plurality of second registers corresponding to a respective first register of the plurality of first registers and configured to latch a value of the counter in response to the value of its respective first register changing from its first value to its second value.

5 . The apparatus of claim 4 , wherein the apparatus is configured to determine a data value stored in a memory cell of the respective string of series-connected memory cells of the respective data line of the respective sensing device of the respective first register of a particular second register of the plurality of second registers in response to a subsequent value of the counter latched in the particular second register.

6 . The apparatus of claim 2 , wherein the counter is a first counter of a plurality of counters of the apparatus, wherein the voltage generation circuit is a first voltage generation circuit of a plurality of voltage generation circuits of the apparatus, and wherein the access line of the plurality of access lines is a first access line of the plurality of access lines, the apparatus further comprising:
a second counter of the plurality of counters; and a second voltage generation circuit of the plurality of voltage generation circuits responsive to an output of the second counter, and having an output selectively connected to a second access line of the plurality of access lines.

7 . The apparatus of claim 6 , wherein the first access line corresponds to an access line of the plurality of access lines selected for a read operation on the plurality of strings of series-connected memory cells, and wherein the second access line corresponds to an access line of the plurality of access lines unselected for the read operation.

8 . The apparatus of claim 6 , wherein the output of the second voltage generation circuit is further selectively connected to at least one additional access line of the plurality of access lines.

9 . The apparatus of claim 8 , wherein each access line of the at least one additional access line of the plurality of access lines corresponds to an access line of the plurality of access lines unselected for the read operation.

10 . A memory, comprising:
an array of memory cells comprising a plurality of strings of series-connected memory cells; a plurality of access lines, each access line of the plurality of access lines connected to a respective memory cell of each string of series-connected memory cells of the plurality of strings of series-connected memory cells; a plurality of data lines, each data line of the plurality of data lines selectively connected to a respective string of series-connected memory cells of the plurality of strings of series-connected memory cells; and a controller for access of the array of memory cells, wherein the controller, during a read operation on the plurality of strings of series-connected memory cells, is configured to cause the memory to:
concurrently increase a respective voltage level applied to each access line of the plurality of access lines during the read operation on the plurality of strings of series-connected memory cells while each data line of the plurality of data lines is connected to its respective string of series-connected memory cells and while each string of series-connected memory cells of the plurality of strings of series-connected memory cells is connected to a common source; and
cease increasing the respective voltage level applied to each access line of the plurality of access lines in response to determining that each data line of the plurality of data lines is connected to the common source through its respective string of series-connected memory cells.

11 . The memory of claim 10 , wherein the controller is further configured to cause the memory to store a representation of the respective voltage level applied to a particular access line of the plurality of access lines at a time of ceasing increasing the respective voltage level applied to each access line of the plurality of access lines in response to determining that each data line of the plurality of data lines is connected to the common source through its respective string of series-connected memory cells.

12 . The memory of claim 11 , wherein the controller is further configured to cause the memory to use the stored representation of the respective voltage level applied to the particular access line to determine a pass voltage for a subsequent read operation on the plurality of strings of series-connected memory cells.

13 . A memory, comprising:
an array of memory cells comprising a plurality of strings of series-connected memory cells selectively connected to a common source; a plurality of access lines, e

Assignees

• Micron Technology Inc

Inventors

• Moschiano Violante
• Ghilardi Tecla
• Vali Tommaso
• Camerlenghi Emilio
• Filipiak William C
• D'Alessandro Andrea

Classifications

• G06F3/0619

  in relation to data integrity, e.g. data losses, bit errors · CPC title

• G11C16/3459

  Circuits or methods to verify correct programming of nonvolatile memory cells · CPC title

• G11C16/26 Primary

  Sensing or reading circuits; Data output circuits · CPC title

• G11C16/0483 Primary

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/30

  Power supply circuits · CPC title