Pin Accessibility Prediction Engine

Patent metadata

Field	Value
Publication number	US-2020364394-A1
Application number	US-202016875844-A
Country	US
Kind code	A1
Filing date	May 15, 2020
Priority date	May 17, 2019
Publication date	Nov 19, 2020
Grant date	—

Abstract

An efficient electronic structure for circuit design, testing and/or manufacture for validating a cell layout design using an intelligent engine trained using selectively arranged cells selected from a cell library. An initial design rule violation (DRV) prediction engine is initially trained using a plurality of pin patterns generated by predefined cell placement combinations, where pin patterns are pixelized and quantified and is classified as either (i) a DRV pin pattern (i.e., pin patterns likely to produce a DRV) or (ii) a DRV-clean pin pattern (i.e., pin patterns unlikely to produce a DRV).

First claim

1 . A pin accessibility prediction engine comprising:
a) a trainable processing engine having a plurality of inputs for receiving input data representing an integrated circuit design pin pattern; and b) a memory for storing values determined through a training process an applied to the trainable processing engine to enable the trainable processing engine to distinguish between input data representing an integrated circuit design pin pattern that is likely to incur a design rule violation upon being routed and input data representing an integrated circuit design pin pattern that is unlikely to incur a design rule violation upon being routed;
the stored values having been determined by a training process in which unrouted pin patterns that are likely to incur a design rule violation upon being routed, unrouted pin patterns that are unlikely to incur a design rule violation upon being routed, routed pin patterns that are likely to incur a design rule violation upon being routed, and routed pin patterns that are unlikely to incur a design rule violation upon being routed are used as a training data set to determine the stored values.

2 . A method for training a pin accessibility prediction engine to enable the pin accessibility prediction engine to distinguish between input data representing an integrated circuit design that is likely to incur a design rule violation upon being routed and input data representing an integrated circuit design that is unlikely to incur a design rule violation upon being routed, the method comprising:
a) generating a plurality of integrated circuit designs; b) selecting for training the pin accessibility prediction engine, from the plurality of integrated circuit designs, input data representing integrated circuit pin patterns that are known to incur a design rule violation upon being routed; c) selecting for training the pin accessibility prediction engine, from the plurality of integrated circuit designs, input data representing integrated circuit pin patterns that are known to not incur a design rule violation upon being routed;
wherein at least some of the training design is taken from a design that will be presented to the pin accessibility engine after training to determine whether the design is likely to incur design rule violations upon being routed.

3 . A method for training a pin accessibility prediction engine comprising:
a) drawing from a cell library a plurality of standard integrated circuit cells; b) combining the cells to form cell combinations; c) generating labeled cell combinations by labeling the cell combinations as being either a DRV cell combination or a non-DRV cell combination; d) using the labeled cell combination to perform an initial training of a trainable prediction engine; e) generating a plurality of queries for cells from the library by routing additional cell combinations, each cell combination based on one of the cells from the library; t) for each cell, applying a plurality of queries to the trainable prediction engine to determine the DRV probability for that cell; g) from the DRV probability, determining a query priority; h) from the query priority, determining a query number, QN that is proportional to the query priority; i) for each cell, applying additional routing queries to the trainable prediction engine to determine the probability that the query has a DRV; j) selecting from the additional routing queries applied to the trainable prediction engine, the QN queries for which the trainable prediction engine was least confident; and k) retraining the trainable prediction engine using the selected QN queries for each cell.

Assignees

• Synopsys Inc

Inventors

• Yu Tao-Chun
• Chiu Hsien-Shih
• Fang Shao-Yun
• Hu Kai-Shun
• Tai Philip Hui-Yuh
• Shen Cindy Chin-Fang
• Sheng Henry

Classifications

• G06N3/047

  Probabilistic or stochastic networks · CPC title

• G06N3/045

  Combinations of networks · CPC title

• G06N3/09

  Supervised learning · CPC title

• G06N3/091

  Active learning · CPC title

• G06N3/0464

  Convolutional networks [CNN, ConvNet] · CPC title