Method for inspecting insertion states of plurality of pins included in connector inserted into substrate, and substrate inspection apparatus

US2020352069A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2020352069-A1
Application numberUS-201816957317-A
CountryUS
Kind codeA1
Filing dateDec 28, 2018
Priority dateDec 28, 2017
Publication dateNov 5, 2020
Grant date

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  1. Title

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  2. Abstract

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  5. First independent claim

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Abstract

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A substrate inspection apparatus may include: a communication circuit; a plurality of light sources; an image sensor; at least one memory; and at least one processor. The processor may be configured to: generate insertion state information indicating an insertion state of each of a plurality of pins included in each of a plurality of first connectors by using the pattern light reflected from the pin tail of each of the plurality of pins; detect at least one second connector having an insertion defect by using the insertion reference information and the insertion state information of each of the plurality of pins; generate a control signal for adjusting at least one first process parameter, based on insertion state information for the plurality of pins included in the at least one second connector; and control the communication circuit to transmit the control signal to the connector insertion apparatus.

First claim

Opening claim text (preview).

What is claimed is: 1 . A substrate inspection apparatus for inspecting insertion states of a plurality of pins included in each of a plurality of connectors inserted into a substrate, comprising: a communication circuit configured to communicate with a connector insertion apparatus for inserting the plurality of connectors including the plurality of pins into the substrate; a plurality of light sources configured to emit pattern light on one surface of a first substrate into which a plurality of first connectors is inserted by the connector insertion apparatus, the plurality of first connectors being inserted into the other surface of the first substrate; an image sensor configured to receive the pattern light reflected from a pin tail of each of the plurality of pins included in each of the plurality of first connectors; at least one memory configured to store insertion reference information indicating a pin tail reference height and a pin tail reference position set for each of the plurality of pins included in each of the plurality of first connectors; and at least one processor, wherein the at least one processor is configured to: generate insertion state information indicating an insertion state of each of the plurality of pins included in each of the plurality of first connectors by using the pattern light reflected from the pin tail of each of the plurality of pins included in each of the plurality of first connectors and received by the image sensor; detect at least one second connector having an insertion defect from among the plurality of first connectors by using the insertion reference information and the insertion state information of each of the plurality of pins included in each of the plurality of first connectors; generate a control signal for adjusting at least one first process parameter among a plurality of process parameters of the connector insertion apparatus, based on the insertion state information of each of the plurality of pins included in the at least one second connector; and control the communication circuit to transmit the control signal to the connector insertion apparatus. 2 . The apparatus of claim 1 , wherein the insertion state information includes information indicating a pin tail height, and information indicating a pin tail position. 3 . The apparatus of claim 1 , wherein the plurality of process parameters includes a process parameter for adjusting a connector insertion force, a process parameter for adjusting a connector insertion position, a process parameter for adjusting a connector insertion speed, and a process parameter for adjusting a movement speed of a connector insertion head used for connector insertion. 4 . The apparatus of claim 1 , wherein the at least one processor is configured to: identify a pin tail reference position of each of the plurality of pins included in each of the plurality of first connectors based on the insertion reference information; identify a pin tail position of each of the plurality of pins included in each of the plurality of first connectors based on the insertion state information; calculate a difference between the pin tail reference position of each of the plurality of pins included in each of the plurality of first connectors and the pin tail position of each of the plurality of pins included in each of the plurality of first connectors; and if at least one connector including at least one pin in which the calculated difference is equal to or greater than a preset first threshold value is detected from among the plurality of first connectors, determine the detected at least one connector as the at least one second connector having the insertion defect. 5 . The apparatus of claim 4 , wherein the at least one processor is configured to: determine at least one process parameter available for adjusting the difference between the pin tail reference position of each of the plurality of pins included in the at least one second connector and the pin tail position of each of the plurality of pins included in the at least one second connector among the plurality of process parameters, as the at least one first process parameter; and generate the control signal for adjusting the at least one first process parameter such that the difference between the pin tail reference position of each of the plurality of pins included in the at least one second connector and the pin tail position of each of the plurality of pins included in the at least one second connector becomes less than the first threshold value. 6 . The apparatus of claim 1 , wherein the at least one processor is configured to: identify a pin tail reference height of each of the plurality of pins included in each of the plurality of first connectors based on the insertion reference information; identify a pin tail height of each of the plurality of pins included in each of the plurality of first connectors based on the insertion state information; calculate a difference between the pin tail reference height of each of the plurality of pins included in each of the plurality of first connectors and the pin tail height of each of the plurality of pins included in each of the plurality of first connectors; and if at least one connector including at least one pin in which the calculated difference is equal to or greater than a preset second threshold value is detected from among the plurality of first connectors, determine the detected at least one connector as the at least one second connector having the insertion defect. 7 . The apparatus of claim 6 , wherein the at least one processor is configured to: determine at least one process parameter available for adjusting the difference between the pin tail reference height of each of the plurality of pins included in the at least one second connector and the pin tail height of each of the plurality of pins included in the at least one second connector among the plurality of process parameters, as the at least one first process parameter; and generate the control signal for adjusting the at least one first process parameter such that the difference between the pin tail reference height of each of the plurality of pins included in the at least one second connector and the pin tail height of each of the plurality of pins included in the at least one second connector becomes less than the second threshold value. 8 . A method for inspecting insertion states of a plurality of pins included in each of a plurality of connectors inserted into a substrate by a substrate inspection apparatus, comprising: emitting pattern light on one surface of a first substrate into which a plurality of first connectors is inserted by a connector insertion apparatus, the plurality of first connectors being inserted into the other surface of the first substrate; receiving the pattern light reflected from a pin tail of each of the plurality of pins included in each of the plurality of first connectors; generating insertion state information indicating an insertion state of each of the plurality of pins included in each of the plurality of first connectors by using the received pattern light reflected from the pin tail of each of the plurality of pins included in each of the plurality of first connectors; detecting at least one second connector having an insertion defect from among the plurality of first connectors by using insertion reference information indicating a pin tail reference height and a pin tail reference position set for each of the plurality of pins included in each of the plurality of first connectors and the insertion state information; generating a control signal for adjusting at least one first process parameter among a plurality of process parameters of

Assignees

Inventors

Classifications

  • Multilead component · CPC title

  • by inserting component lead or terminal into base aperture · CPC title

  • by utilizing optical sighting device · CPC title

  • Height gauges · CPC title

  • Quality monitoring using results from monitoring devices, e.g. feedback loops (H05K13/084 takes precedence) · CPC title

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What does patent US2020352069A1 cover?
A substrate inspection apparatus may include: a communication circuit; a plurality of light sources; an image sensor; at least one memory; and at least one processor. The processor may be configured to: generate insertion state information indicating an insertion state of each of a plurality of pins included in each of a plurality of first connectors by using the pattern light reflected from th…
Who is the assignee on this patent?
Koh Young Tech Inc
What technology area does this patent fall under?
Primary CPC classification H01R43/205. Mapped technology areas include Electricity.
When was this patent published?
Publication date Thu Nov 05 2020 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).