Virtual pipe for connecting devices

Patent metadata

Field	Value
Publication number	US-2020349096-A1
Application number	US-201916402092-A
Country	US
Kind code	A1
Filing date	May 2, 2019
Priority date	May 2, 2019
Publication date	Nov 5, 2020
Grant date	—

Abstract

A universal protocol engine circuit aggregates data of multiple communication ports that may use different communication protocols according to a configurable communication protocol. In a transmitter mode, the universal protocol engine circuit references a slot table defining a sequence of the ports to generate output data from the input data received from the ports, and transmits the output data over a wired or wireless communication link. In a receiver mode, the universal protocol engine circuit references the slot table to parse input data from the communication link into output data for each of the ports. The sequence of ports of the slot table may be configurable according to the speed or other properties of the communication ports.

First claim

What is claimed is:

1 . An electronic device, comprising:
a universal protocol engine circuit, including:
a memory configured to store a slot table defining a sequence of ports in which data from one or more communication ports are to be transmitted, each of the communication ports associated with a corresponding communication protocol;
an aggregator circuit coupled to the memory, the aggregator circuit configured to:
receive input data from the one or more communication ports according to the corresponding communication protocol; and
generate output data by selecting the input data from the one or more communication ports according to the sequence of the ports defined in the slot table; and

a transmitter configured to generate an output stream from the output data and provide the output stream to a wired or wireless coupler for transmission to another electronic device.

2 . The electronic device of claim 1 , wherein:
the sequence of ports in the slot table indicates one or more selections of a first port mixed with one or more selections of a second port; and the aggregator circuit selects first data from the first port when the slot table indicates selection of the first port and selects second data from the second port when the slot table indicates selection of the second port to generate the output data according to the sequence of ports.

3 . The electronic device of claim 1 , wherein a first communication protocol associated with a first port of the one or more communication ports is configured for data communication at a higher speed than a second communication protocol associated with a second port of the one or more communication ports, and the output data includes first input data of the first port mixed with second input data of the second port according to the sequence of ports.

4 . The electronic device of claim 1 , wherein the universal protocol engine circuit further includes an encoder circuit configured to encode the output data from the aggregator circuit prior to generation of the output stream by the transmitter using the output data.

5 . The electronic device of claim 1 , wherein the universal protocol engine circuit further includes an encrypter circuit configured to encrypt the output data from the aggregator circuit prior to generation of the output stream by the transmitter using the output data.

6 . The electronic device of claim 1 , wherein the universal protocol engine circuit further includes an error correction circuit configured to apply error correction to the output data prior to generation of the output stream from the aggregator circuit prior to generation of the output stream by the transmitter using the output data.

7 . The electronic device of claim 1 , wherein a first communication protocol associated with a first port of the one or more communication ports is configured for data communication at a higher speed than a second communication protocol associated with a second port of the one or more communication ports, and the first port has a higher frequency of selection in the sequence of ports than the second port.

8 . The electronic device of claim 1 , wherein the universal protocol engine circuit further includes:
a receiver configured to receive an input stream from the wired or wireless coupler and generate other input data from the input stream; and a parser circuit coupled to the memory and the receiver, the parser circuit configured to:
receive the other input data from the receiver; and
generate other output data for each of the one or more communication ports from the other input data according to the sequence of the ports defined in the slot table or another sequence of the ports defined in another slot table stored in the memory.

9 . The electronic device of claim 8 , wherein:
the sequence of ports defined in the slot table or the other sequence of ports defined in the other slot table indicates one or more selections of a first port mixed with one or more selections of a second port; and the parser circuit assigns first data to the first port when the slot table indicates selection of the first port and assigns second data to the second port when the slot table indicates selection of the second port to generate the other output data according to the sequence of ports.

10 . The electronic device of claim 8 , wherein the universal protocol engine circuit further includes a decoder circuit configured to decode the other input data from the receiver prior to generation of the other output data by the parser circuit using the other input data.

11 . The electronic device of claim 8 , wherein the universal protocol engine circuit further includes a decrypter circuit configured to decrypt the other input data from the receiver prior to generation of the other output data by the parser circuit using the other input data.

12 . The electronic device of claim 8 , wherein the universal protocol engine circuit further includes an error correction circuit configured to apply error correction to the other input data from the receiver prior to generation of the other output data by the parser circuit using the other input data.

13 . The electronic device of claim 1 , further comprising:
another universal protocol engine circuit configured to transfer data through another wired or wireless coupler according to another sequence of ports stored in another slot table; and a configurable crossbar coupled to the one or more communication ports, the universal protocol engine circuit and the other universal protocol engine circuit, the configurable crossbar configured to:
connect at least one of the one or more communication ports to the universal protocol engine circuit according to the slot table; and
connect at least another one of the one or more communication ports to the other universal protocol engine circuit according to the other slot table.

14 . The electronic device of claim 13 , wherein the universal protocol engine circuit operates in a transmitter mode in parallel with the other universal protocol engine circuit operating in a receiver mode.

15 . The electronic device of claim 1 , further comprising a circuit board including:
a processor configured to generate the input data and provide the input data to the universal protocol engine circuit via the one or more communication ports; and the universal protocol engine circuit, wherein the universal protocol engine circuit further includes virtual contactless physical layers (VcPHYs) configured to receive the input data from the one or more communication ports.

16 . The electronic device of claim 1 , further comprising:
a first circuit board including a processor configured to generate the input data and provide the input data to the universal protocol engine circuit via the one or more communication ports; and a second circuit board including the universal protocol engine circuit, wherein the universal protocol engine circuit further includes physical layers (PHYs) configured to receive the input data from the one or more communication ports.

17 . The electronic device of claim 1 , wherein the coupler is a wireless extremely high frequency (EHF) coupler.

18 . An electronic device, comprising:
a universal protocol engine circuit, including:
a memory configured to store a slot table defining a sequence of ports in which data received from another electronic device are to be provided to one or more communication ports, each of the communication ports associated with a corresponding communication protocol;
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Assignees

• Keyssa Systems Inc

Inventors

• Isaac Roger Dwain
• Ruberg Alan T
• Cuppett Jeff
• Pak Edward

Classifications

• H04L69/18

  Multiprotocol handlers, e.g. single devices capable of handling multiple protocols · CPC title

• H04L69/14

  Multichannel or multilink protocols · CPC title

• H04L69/12 Primary

  Protocol engines · CPC title

• H04L1/0045

  Arrangements at the receiver end · CPC title

• G06F13/1668 Primary

  Details of memory controller · CPC title