Semiconductor device and memory reading method

Patent metadata

Field	Value
Publication number	US-2020327921-A1
Application number	US-202016828545-A
Country	US
Kind code	A1
Filing date	Mar 24, 2020
Priority date	Apr 10, 2019
Publication date	Oct 15, 2020
Grant date	—

Abstract

A semiconductor device capable of enlarging a read margin of a memory cell and a method of surrounding a read of a memory are provided. The reference word line RWL is activated in a time division manner with respect to the plurality of word lines WL. The precharge circuit PRE applies the read potential VRD to the bit line BL, and the precharge circuit PRE flows the read current Icel from the selected memory cell MC and the read reference current Iref from the reference cell RC to the bit line BL in a time division manner. A detection currents Ird2a, Irr2a, each of which is a current proportional to the current flowing through the bitline BL, flows through the current detection line CDL.

First claim

What is claimed is:

1 . A semiconductor device comprising:
a plurality of word lines; a bit line; a plurality of memory cells arranged at intersections of the word lines and the bit line, and selected by the word lines; a reference word line activated in time division manner for the word lines; a reference cell arranged at an intersection of the reference word line and the bit line, and selected by the reference word line;
a precharge circuit configured to apply a reading voltage to the bit line, and configured to send a reading current from a selected memory cell selected by one of the word lines and a reading reference current from the reference cell in the time division manner;
a current detection line through which a detection current which is proportional to a current flowing the bit line flows; and
a current comparing circuit connected to the current detection line, and configured to compare the detection current and the reading reference current.

2 . The semiconductor device according to claim 1 , wherein the precharge circuit comprises:
a first transistor whose current path is arranged between a first power supply and the bit line; and a bias control circuit configured to feedback control a control voltage of the first transistor by inputting a voltage of the bit line and a predetermined reference voltage.

3 . The semiconductor device according to claim 2 , further comprising a second transistor whose current path is arranged between the first power supply and the current detection line, and configured to receive the control voltage of the first transistor.

4 . The semiconductor device according to claim 3 , wherein a ratio of a gate width and a gate length of the second transistor is smaller than that of the first transistor.

5 . The semiconductor device according to claim 2 , wherein the bias control circuit comprises a differential amplifier circuit configured to feedback control the control voltage of the first transistor so that the voltage of the bit line matches to the reference voltage.

6 . The semiconductor device according to claim 2 , wherein the bias control circuit comprises:
a third transistor whose current path is arranged between the bit line and a control terminal of the first transistor, and having a control terminal applied the reference voltage; and a first constant current source arranged between the third transistor and a second power supply, and configured to flow a load current to the third transistor.

7 . The semiconductor device according to claim 6 , further comprising a reference voltage generating circuit configured to generate the reference voltage,
wherein the reference voltage generating circuit comprises:
a fourth transistor arranged between the first power supply and the control terminal of the third transistor, and composed of diode connection, and
a second constant current source arranged between the fourth transistor and the second power supply, and configured to flow a constant current to the fourth transistor.

8 . The semiconductor device according to claim 3 ,
wherein the current comparison circuit comprises: a third transistor whose current path is arranged between the current detection line and a second power supply; a switch configured to change a connection of the third transistor to a diode connection when activated; and a capacitor element configured to retain a control voltage of the third transistor.

9 . The semiconductor device according to claim 8 ,
wherein the switch is a MOS transistor, and wherein an activation of the switch is controlled by a switch control signal having a voltage amplitude larger than a voltage difference between the first power supply and the second power supply.

10 . The semiconductor device according to claim 2 ,
wherein the first transistor is a p-channel MOS transistor, and wherein the precharge circuit changes the reading voltage to a voltage lower than a voltage of the first power supply by a saturation drain voltage of the first transistor.

11 . The semiconductor device according to claim 1 ,
wherein the bit line comprises:
a plurality of local bit lines; and
a global bit line provided in common to the plurality of the local bit lines and connected to one of the plurality of local bit lines via a bit line selection switch,
wherein the plurality of the local bit lines are connected to the plurality of the memory cells respectively, wherein the global bit line is connected to the reference cell, and wherein the global bit receives the reading current from the selected memory cell and a reading reference current from the reference cell in the time division manner when a selected one of the plurality of the local bit line is connected to the global bit line.

12 . The semiconductor device according to claim 1 , wherein the memory cells are flash memory cells.

13 . A method for reading data of a memory, comprising:
(a) flowing a reading current from a selected memory cell to a first current path by applying a reading voltage to the selected memory cell via the first current path; (b) flowing a reading reference current from a reference cell to the first current path; (c) store one of a first detection current which is proportional to the reading current or a second detection current which is proportional to the reading reference current via the second current path as a memory current; and (d) comparing another one of a first detection current which is proportional to the reading current or a second detection current which is proportional to the reading reference current with the memory current.

14 . A method according to claim 13 ,
wherein (a) and (b) is performed by a precharge circuit having a current source composed of a MOS transistor, and wherein the reading voltage is lower than a power supply voltage by a saturation drain voltage of the MOS transistor.

15 . A method according to claim 13 ,
wherein a current flowing through the second current path is smaller than that of the first current path.

16 . A method according to claim 13 ,
wherein the first current path having:
a local bit line connected to a plurality of memory cells; and
a global bit line connected to the reference cell and the precharge circuit,
wherein, at performing (a) and (b), the local bit line and the global bit line is connected via a bit line selecting circuit.

17 . A method according to claim 13 , wherein the memory is a flash memory.

Assignees

• Renesas Electronics Corp

Inventors

• Takeda Koichi

Classifications

• G11C16/28

  using differential sensing or reference cells, e.g. dummy cells · CPC title

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title

• G11C16/24

  Bit-line control circuits · CPC title

• G11C16/0408

  comprising cells containing floating gate transistors (G11C16/0483, G11C16/0491 take precedence) · CPC title

• G11C16/02

  electrically programmable · CPC title