Automated Self-Check of a Closed Loop Emulation Replay

Patent metadata

Field	Value
Publication number	US-2020327027-A1
Application number	US-202016846710-A
Country	US
Kind code	A1
Filing date	Apr 13, 2020
Priority date	Apr 11, 2019
Publication date	Oct 15, 2020
Grant date	—

Abstract

A configuration for testing a design of an electronic circuit during a set of clock cycles. The test output of the emulation of a design is filtered based on a received testcase. To filter the test output, for each clock cycle in the testcase, a list of objects associated with a previous clock cycle in test case is identified. One or more objects associated with the one or more commands to be executed during the clock cycle is also identified. An updated list is generated by augmenting the list of objects associated with the previous clock cycle with the one or more objects associated with the one or more commands to be executed during the clock cycle. Output values for objects included in the updated list of objects is selected. The filtered test output is then stored in an activity database.

First claim

What is claimed is:

1 . A method for testing a design of an electronic circuit during a plurality of clock cycles, the method comprising:
receiving a testcase identifying a subset of clock cycles of the plurality of clock cycles, and one or more commands to be executed during each clock cycle of the subset of clock cycles; receiving a test output for the design of the electronic circuit based on the received testcase, the test output including output values for each object of interest of the design during each clock cycle of the plurality of clock cycles; filtering the test output based on the received testcase, comprising, for each clock cycle of the subset of clock cycles of the testcase:
identifying a list of objects of interest associated with a previous clock cycle in the subset of clock cycles of the testcase,
identifying one or more objects of interest associated with the one or more commands to be executed during the clock cycle,
generating an updated list of objects of interest by adding the identified one or more objects of interest to the list of objects of interest associated with the previous clock cycle, and
selecting output values for objects of interest included in the updated list of objects of interest; and
storing the filtered test output.

2 . The method of claim 1 , wherein the objects of interest of the design of the electronic circuit comprises one or more of logic gates, one or more memory elements, one or more interfaces, and one or more signal access points.

3 . The method of claim 1 , further comprising:
receiving a second test output for a second design of the electronic circuit based on a second testcase, filtering the second test output based on the second testcase; determining whether the filtered test output differs from the filtered second test output; and providing an indication of a mismatch between the filtered test output and the filtered second test output to a user.

4 . The method of claim 3 , wherein the second testcase is the same as the first testcase, and the first design is the same as the second design of the electronic circuit.

5 . The method of claim 3 , wherein determining whether the filtered test output differs from the filtered second test output comprises:
for each output value in the filtered test output, determining if the output value in the filtered test output matches a corresponding output value in the filtered second test output.

6 . The method of claim 5 , wherein providing an indication of a mismatch between the filtered test output and the filtered second test output to a user comprises:
for each mismatching output value, displaying an object identifier associated with the mismatching output value, a time associated with the mismatching output value, the output value in the filtered test output, the corresponding output value in the filtered second test output, and an activity type information associated with the mismatching output value.

7 . The method of claim 1 , wherein storing the filtered test output comprises, for each clock cycle of the subset of clock cycles of the testcase comprises:
storing at least the selected output values and an activity type information for objects of interest included in the updated list of objects of interest.

8 . The method of claim 1 , wherein generating an updated list of objects of interest by adding the identified one or more objects of interest to the list of objects of interest associated with the previous clock cycle comprises:
for each object of interest in the identified one or more objects of interest, determining whether the object of interest is included in the list of objects of interest associated with the previous clock cycle; and responsive to determining that the object of interest is not included in the list of objects of interest associated with the previous clock cycle, adding the object of interest to the list of objects of interest associated with the previous clock cycle.

9 . The method of claim 1 , wherein receiving the test output for the design of the electronic circuit comprises:
performing an emulation of the design of the electronic circuit during based on the received test case; and recording signal values at each netlist of the design during each clock cycle of the plurality of clock cycles.

10 . The method of claim 9 , wherein performing an emulation of the design of the electronic circuit comprises receiving a manual input through an interface, and wherein filtering the test output further comprises:
identifying a clock cycle when the manual input was received; adding the identified clock cycle to the subset of clock cycles; identifying a list of objects of interest associated with a clock cycle in the subset of clock cycles preceding the identified clock cycle; generating an updated list of objects of interest for the identified clock cycle by:
adding one or more objects of interest associated with the interface to the list of objects of interest associated with the clock cycle in the subset of clock cycles preceding the identified clock cycle, and
selecting output values for objects of interest included in the updated list of objects of interest for the identified clock cycle.

11 . The method of claim 1 , wherein filtering the test output further comprises:
Filtering out, for each clock cycle of the subset of clock cycles of the testcase, output values for objects of interest not included in the updated list of objects of interest; and filtering out output values associated with clock cycles not included in the subset of clock cycles of the test case.

12 . A non-transitory computer readable storage medium comprising stored instructions for testing a design of an electronic circuit during a plurality of clock cycles, the instructions when executed by a processor cause the processor to:
receive a testcase identifying a subset of clock cycles of the plurality of clock cycles, and one or more commands to be executed during each clock cycle of the subset of clock cycles; receive a test output for the design of the electronic circuit based on the received testcase, the test output including output values for each object of interest of the design during each clock cycle of the plurality of clock cycles; filter the test output based on the received testcase, wherein the instructions for filtering the test out further causes the processor to, for each clock cycle of the subset of clock cycles of the testcase:
identify a list of objects of interest associated with a previous clock cycle in the subset of clock cycles of the testcase,
identify one or more objects of interest associated with the one or more commands to be executed during the clock cycle,
generate an updated list of objects of interest by adding the identified one or more objects of interest to the list of objects of interest associated with the previous clock cycle, and
select output values for objects of interest included in the updated list of objects of interest; and
store the filtered test output.

13 . The non-transitory computer readable storage medium of claim 12 , further comprising stored instructions that when executed causes the processor to:
receive a second test output for a second design of the electronic circuit based on a second testcase, filter the second test output based on the second testcase; determine whether the filtered test output differs from the filtered second test output; and provide an indication of a mismatch between the filtered test output and the filtered second test output to a user.

14 . The non-transitory computer readable storage m

Assignees

• Synopsys Inc

Inventors

• Mittal Ribhu
• Prasad Vivek

Classifications

• G06F11/263

  Generation of test inputs, e.g. test vectors, patterns or sequences {; with adaptation of the tested hardware for testability with external testers} · CPC title

• G06F30/331 Primary

  with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation · CPC title

• G06F11/2733

  Test interface between tester and unit under test · CPC title

• G06F11/27

  Built-in tests · CPC title

• G06F11/261 Primary

  by simulating additional hardware, e.g. fault simulation · CPC title