Data storage device and system with interruption optimization

Patent metadata

Field	Value
Publication number	US-2020326883-A1
Application number	US-201916415015-A
Country	US
Kind code	A1
Filing date	May 17, 2019
Priority date	Apr 9, 2019
Publication date	Oct 15, 2020
Grant date	—

Abstract

A data storage device with interruption optimization having a non-volatile memory and a controller is shown. The controller operates the non-volatile memory in response to a host. The controller has a buffer which is filled with an interrupt delay that is evaluated by the host according to the status of the central processing unit of the host. The controller delays sending an interrupt request to the host according to the interrupt delay.

First claim

What is claimed is:

1 . A data storage device, comprising:
a non-volatile memory; and a controller, operating the non-volatile memory in response to a host, wherein: the controller has a buffer which stores an interrupt delay that is evaluated by the host according to a status of a central processing unit of the host; and the controller delays sending an interrupt request to the host according to the interrupt delay.

2 . The data storage device as claimed in claim 1 , wherein:
when the controller sends a first interrupt request to the host, a driver of the host checks whether the central processing unit is awakened from an idle loop or has been interrupted from performing a task, and thereby adjusts the interrupt delay to delay a second interrupt request.

3 . The data storage device as claimed in claim 2 , wherein:
after the central processing unit completes an overhead period and a working period corresponding to the first interrupt request, the controller is not permitted to issue the second interrupt request until the interrupt delay is satisfied.

4 . The data storage device as claimed in claim 3 , wherein:
when the central processing unit wakes from an idle loop, the interrupt delay is shortened by a first adjustment amount; and when the central processing unit is interrupted from performing a task, the interrupt delay is increased by a second adjustment amount.

5 . The data storage device as claimed in claim 4 , wherein the first adjustment amount is greater than the second adjustment amount.

6 . The data storage device as claimed in claim 4 , wherein the interrupt delay has an upper limit.

7 . The data storage device as claimed in claim 3 , wherein:
when the overhead period is completed, the driver prompts the controller to mark events queued in a queue; the central processing unit completes the marked events during the working period; and when the interrupt delay has been satisfied and there are any unmarked events in the queue, the controller sends the second interrupt request.

8 . The data storage device as claimed in claim 3 , wherein:
when the working period is completed, the driver provides the interrupt delay to be filled into the buffer of the controller, and the controller determines a transmission time point of the second interrupt request according to the interrupt delay.

9 . A data storage system, comprising:
a host; and a data storage device comprising a non-volatile memory and a controller, wherein: the controller operates the non-volatile memory in response to the host, the host has a central processing unit and runs a driver; according to a status of the central processing unit, the driver issues an interrupt delay to the data storage device; and the controller delays sending an interrupt request to the host according to the interrupt delay.

10 . The data storage system as claimed in claim 9 , wherein:
when the controller sends a first interrupt request to the host, the driver of the host checks whether the central processing unit is awakened from an idle loop or is interrupted from performing a task, and thereby adjusts the interrupt delay to delay a second interrupt request.

11 . The data storage system as claimed in claim 10 , wherein:
after the central processing unit completes an overhead period and a working period corresponding to the first interrupt request, the controller is not permitted to issue the second interrupt request until the interrupt delay is satisfied.

12 . The data storage system as claimed in claim 11 , wherein:
when the central processing unit wakes from an idle loop, the interrupt delay is shortened by a first adjustment amount; and when the central processing unit is interrupted from performing a task, the interrupt delay is increased by a second adjustment amount.

13 . The data storage system as claimed in claim 12 , wherein the first adjustment amount is greater than the second adjustment amount.

14 . The data storage system as claimed in claim 12 , wherein the interrupt delay has an upper limit.

15 . The data storage system as claimed in claim 11 , wherein:
when the overhead period is completed, the driver prompts the controller to mark events queued in a queue; the central processing unit completes the marked events during the working period; and when the interrupt delay has been satisfied and there are any unmarked events in the queue, the controller sends the second interrupt request.

16 . The data storage system as claimed in claim 11 , wherein:
the controller has a buffer to be filled with the interrupt delay; and when the working period is completed, the driver provides the interrupt delay to be filled into the buffer, and the controller determines a transmission time point of the second interrupt request according to the interrupt delay.

Assignees

• Shannon Systems Ltd

Inventors

• Zhou Zhen

Classifications

• G06F9/4812 Primary

  by interrupt, e.g. masked · CPC title

• G06F3/0604

  Improving or facilitating administration, e.g. storage management · CPC title

• G06F3/0659 Primary

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G06F3/0679 Primary

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title