All solid battery

US2020313232A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2020313232-A1
Application numberUS-202016819836-A
CountryUS
Kind codeA1
Filing dateMar 16, 2020
Priority dateMar 28, 2019
Publication dateOct 1, 2020
Grant date

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  1. Title

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  2. Abstract

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  4. Key dates

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  5. First independent claim

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

An all solid battery includes: a multilayer chip in which each of solid electrolyte layers and each of electrodes are alternately stacked, a main component of the solid electrolyte layers being phosphoric acid salt-based solid electrolyte, the plurality of electrodes being alternately exposed to a first end face and a second end face of the multilayer chip, a first external electrode provided on the first end face; a second external electrode provided on the second end face; and wherein L/W is 0.2 or more and 1.1 or less, when a length of the multilayer chip in a first direction in which the first end face faces with the second end face is L, and a width of the multilayer chip in a second direction that is vertical to the first direction and a stacking direction of the multilayer chip is W.

First claim

Opening claim text (preview).

What is claimed is: 1 . An all solid battery comprising: a multilayer chip in which each of a plurality of solid electrolyte layers and each of a plurality of electrodes are alternately stacked, a main component of the solid electrolyte layers being phosphoric acid salt-based solid electrolyte, the multilayer chip having a rectangular parallelepiped shape, the plurality of electrodes being alternately exposed to a first end face and a second end face of the multilayer chip, the first end face facing with the second end face, a first external electrode provided on the first end face; a second external electrode provided on the second end face; and wherein L/W is 0.2 or more and 1.1 or less, when a length of the multilayer chip in a first direction in which the first end face faces with the second end face is L, and a width of the multilayer chip in a second direction that is vertical to the first direction and a stacking direction of the multilayer chip is W. 2 . The all solid battery as claimed in claim 1 , wherein the L/W is 0.5 or more and 1.0 or less. 3 . The all solid battery as claimed in claim 1 , wherein (L+W)/T is 3 or more and 85 or less, when a thickness of the multilayer chip in the stacking direction is T. 4 . The all solid battery as claimed in claim 1 , wherein the plurality of electrodes have a structure in which an electric collector layer is sandwiched by two electrode layers including an electrode active material, wherein an average thickness of electric collector layers of the plurality of electrodes is 10 μm or less. 5 . The all solid battery as claimed in claim 4 , wherein the average thickness of electric collector layers of the plurality of electrodes is 0.5 μm or more and 5 μm or less. 6 . The all solid battery as claimed in claim 1 , wherein an average thickness of the plurality of solid electrolyte layers is 10 μm or less. 7 . The all solid battery as claimed in claim 6 , wherein the average thickness of the plurality of solid electrolyte layers is 0.5 μm or more and 5 μm or less. 8 . The all solid battery as claimed in claim 1 , wherein the phosphoric acid salt-based solid electrolyte has a NASICON structure.

Assignees

Inventors

Classifications

  • Fixed electrical connections, i.e. not intended for disconnection · CPC title

  • having a chip structure, e.g. micro-sized batteries integrated on chips · CPC title

  • Manufacturing or production processes characterised by the final manufactured product · CPC title

  • Solid materials · CPC title

  • of accumulators with folded construction elements except wound ones, i.e. folded positive or negative electrodes or separators, e.g. with "Z"-shaped electrodes or separators · CPC title

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What does patent US2020313232A1 cover?
An all solid battery includes: a multilayer chip in which each of solid electrolyte layers and each of electrodes are alternately stacked, a main component of the solid electrolyte layers being phosphoric acid salt-based solid electrolyte, the plurality of electrodes being alternately exposed to a first end face and a second end face of the multilayer chip, a first external electrode provided o…
Who is the assignee on this patent?
Taiyo Yuden Kk
What technology area does this patent fall under?
Primary CPC classification H01M10/0562. Mapped technology areas include Electricity.
When was this patent published?
Publication date Thu Oct 01 2020 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).