Solid-state structures with volatile sintering aids, and methods for fabrication and use thereof
US-2024429439-A1 · Dec 26, 2024 · US
US2020313232A1 · US · A1
| Field | Value |
|---|---|
| Publication number | US-2020313232-A1 |
| Application number | US-202016819836-A |
| Country | US |
| Kind code | A1 |
| Filing date | Mar 16, 2020 |
| Priority date | Mar 28, 2019 |
| Publication date | Oct 1, 2020 |
| Grant date | — |
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An all solid battery includes: a multilayer chip in which each of solid electrolyte layers and each of electrodes are alternately stacked, a main component of the solid electrolyte layers being phosphoric acid salt-based solid electrolyte, the plurality of electrodes being alternately exposed to a first end face and a second end face of the multilayer chip, a first external electrode provided on the first end face; a second external electrode provided on the second end face; and wherein L/W is 0.2 or more and 1.1 or less, when a length of the multilayer chip in a first direction in which the first end face faces with the second end face is L, and a width of the multilayer chip in a second direction that is vertical to the first direction and a stacking direction of the multilayer chip is W.
Opening claim text (preview).
What is claimed is: 1 . An all solid battery comprising: a multilayer chip in which each of a plurality of solid electrolyte layers and each of a plurality of electrodes are alternately stacked, a main component of the solid electrolyte layers being phosphoric acid salt-based solid electrolyte, the multilayer chip having a rectangular parallelepiped shape, the plurality of electrodes being alternately exposed to a first end face and a second end face of the multilayer chip, the first end face facing with the second end face, a first external electrode provided on the first end face; a second external electrode provided on the second end face; and wherein L/W is 0.2 or more and 1.1 or less, when a length of the multilayer chip in a first direction in which the first end face faces with the second end face is L, and a width of the multilayer chip in a second direction that is vertical to the first direction and a stacking direction of the multilayer chip is W. 2 . The all solid battery as claimed in claim 1 , wherein the L/W is 0.5 or more and 1.0 or less. 3 . The all solid battery as claimed in claim 1 , wherein (L+W)/T is 3 or more and 85 or less, when a thickness of the multilayer chip in the stacking direction is T. 4 . The all solid battery as claimed in claim 1 , wherein the plurality of electrodes have a structure in which an electric collector layer is sandwiched by two electrode layers including an electrode active material, wherein an average thickness of electric collector layers of the plurality of electrodes is 10 μm or less. 5 . The all solid battery as claimed in claim 4 , wherein the average thickness of electric collector layers of the plurality of electrodes is 0.5 μm or more and 5 μm or less. 6 . The all solid battery as claimed in claim 1 , wherein an average thickness of the plurality of solid electrolyte layers is 10 μm or less. 7 . The all solid battery as claimed in claim 6 , wherein the average thickness of the plurality of solid electrolyte layers is 0.5 μm or more and 5 μm or less. 8 . The all solid battery as claimed in claim 1 , wherein the phosphoric acid salt-based solid electrolyte has a NASICON structure.
Fixed electrical connections, i.e. not intended for disconnection · CPC title
having a chip structure, e.g. micro-sized batteries integrated on chips · CPC title
Manufacturing or production processes characterised by the final manufactured product · CPC title
Solid materials · CPC title
of accumulators with folded construction elements except wound ones, i.e. folded positive or negative electrodes or separators, e.g. with "Z"-shaped electrodes or separators · CPC title
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