All-solid battery

US2020313230A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2020313230-A1
Application numberUS-202016780414-A
CountryUS
Kind codeA1
Filing dateFeb 3, 2020
Priority dateMar 28, 2019
Publication dateOct 1, 2020
Grant date

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

An all-solid battery includes: a multilayer chip having a substantially rectangular parallelepiped shape and including solid electrolyte layers and electrodes alternately stacked, the electrodes being alternately exposed to two edge faces facing each other of the multilayer chip, wherein cover layers are provided between two faces, which face in a stacking direction of the solid electrolyte layers and the electrodes, of four faces other than the two edge faces of the multilayer chip and a cell reaction region where two adjacent electrodes exposed to different edge faces face each other across the solid electrolyte layer, and an active material layer containing an electrode active material is provided between the cover layers and the cell reaction region, no cell reaction occurring between the active material layer and an outermost electrode in the cell reaction region, the solid electrolyte layer being located between the active material layer and the cell reaction region.

First claim

Opening claim text (preview).

What is claimed is: 1 . An all-solid battery comprising: a multilayer chip having a substantially rectangular parallelepiped shape and including solid electrolyte layers and electrodes that are alternately stacked, the electrodes being alternately exposed to two edge faces facing each other of the multilayer chip, the solid electrolyte layers being mainly composed of phosphoric acid salt-based solid electrolyte; and a pair of external electrodes provided on the two edge faces, wherein a pair of cover layers is provided between two faces of four faces other than the two edge faces of the multilayer chip and a cell reaction region, the two faces facing in a stacking direction of the solid electrolyte layers and the electrodes, the cell reaction region being a region where two adjacent electrodes, which are exposed to different edge faces, face each other across the solid electrolyte layer, and an active material layer is provided between the pair of cover layers and the cell reaction region, the active material layer containing an electrode active material, no cell reaction occurring between the active material layer and an outermost electrode of the electrodes in the cell reaction region, the solid electrolyte layer being located between the active material layer and the cell reaction region. 2 . The all-solid battery according to claim 1 , wherein the electrodes have a structure in which a current collector layer is sandwiched between two electrode layers containing an electrode active material. 3 . The all-solid battery according to claim 2 , wherein the active material layer contains the electrode active material contained in the electrode layer of the outermost electrode in the cell reaction region. 4 . The all-solid battery according to claim 1 , wherein the active material layer has a structure identical to a structure of the outermost electrode in the cell reaction region. 5 . The all-solid battery according to claim 4 , wherein an average thickness of each layer of the dummy electrode is identical to an average thickness of a corresponding layer of the outermost electrode in the cell reaction region. 6 . The all-solid battery according to claim 1 , wherein the active material layer includes a first active material layer and a second active material layer, the first active material layer being located between the cover layer closer to a first face of the two faces facing each other and the cell reaction region, the first active material layer not being connected to at least an external electrode different from an external electrode to which an electrode closest to the first face among the electrodes included in the cell reaction region is connected, the second active material layer being located between the cover layer closer to a second face of the two faces facing each other and the cell reaction region, the second active material layer not being connected to at least an external electrode different from an external electrode to which an electrode closest to the second face among the electrodes included in the cell reaction region is connected. 7 . The all-solid battery according to claim 1 , wherein the active material layer is connected to none of the pair of external electrodes. 8 . The all-solid battery according to claim 1 , wherein a distance between the active material layer and the outermost electrode in the cell reaction region in the stacking direction is substantially equal to an average thickness in the thickness direction of the solid electrolyte sandwiched between the electrodes exposed to the different edge faces in the cell reaction region. 9 . The all-solid battery according to claim 1 , wherein the cover layer is mainly composed of the phosphoric acid salt-based solid electrolyte identical to a main component of the solid electrolyte layer. 10 . The all-solid battery according to claim 1 , wherein the phosphoric acid salt-based solid electrolyte has a NASICON structure.

Assignees

Inventors

Classifications

  • Inorganic material · CPC title

  • on opposite sides of the cell · CPC title

  • having a chip structure, e.g. micro-sized batteries integrated on chips · CPC title

  • inorganic · CPC title

  • Inorganic material · CPC title

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What does patent US2020313230A1 cover?
An all-solid battery includes: a multilayer chip having a substantially rectangular parallelepiped shape and including solid electrolyte layers and electrodes alternately stacked, the electrodes being alternately exposed to two edge faces facing each other of the multilayer chip, wherein cover layers are provided between two faces, which face in a stacking direction of the solid electrolyte lay…
Who is the assignee on this patent?
Taiyo Yuden Kk
What technology area does this patent fall under?
Primary CPC classification H01M10/0562. Mapped technology areas include Electricity.
When was this patent published?
Publication date Thu Oct 01 2020 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).